Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8367543 | Structure and method to improve current-carrying capabilities of C4 joints | Mukta G. Farooq, Jasvir Singh Jaspal, William Francis Landers, Thomas E. Lombardi, Hai P. Longworth +1 more | 2013-02-05 |
| 7821120 | Metal filled through via structure for providing vertical wafer-to-wafer interconnection | Roy Yu | 2010-10-26 |
| 7564118 | Chip and wafer integration process using vertical connections | Roy Yu, Chandrika Prasad, Chandrasekhar Narayan | 2009-07-21 |
| 7388277 | Chip and wafer integration process using vertical connections | Roy Yu, Chandrika Prasad, Chandrasekhar Narayan | 2008-06-17 |
| 7354798 | Three-dimensional device fabrication method | Roy Yu | 2008-04-08 |
| 7344959 | Metal filled through via structure for providing vertical wafer-to-wafer interconnection | Roy Yu | 2008-03-18 |
| 7071031 | Three-dimensional integrated CMOS-MEMS device and process for making the same | Michel Despont, Ute Drechsler, Peter Vettiger, Roy Yu | 2006-07-04 |
| 7049697 | Process for making fine pitch connections between devices and structure made by the process | Chandrika Prasad, Roy Yu | 2006-05-23 |
| 7049695 | Method and device for heat dissipation in semiconductor modules | — | 2006-05-23 |
| 6864165 | Method of fabricating integrated electronic chip with an interconnect device | Chandrika Prasad, Roy Yu | 2005-03-08 |
| 6856025 | Chip and wafer integration process using vertical connections | Roy Yu, Chandrika Prasad, Chandrasekhar Narayan | 2005-02-15 |
| 6835589 | Three-dimensional integrated CMOS-MEMS device and process for making the same | Michel Despont, Ute Drechsler, Chandrika Prasad, Peter Vettiger, Roy Yu | 2004-12-28 |
| 6737297 | Process for making fine pitch connections between devices and structure made by the process | Chandrika Prasad, Roy Yu | 2004-05-18 |
| 6730529 | Method for chip testing | Howard L. Kalter, George S. Prokop, Donald L. Wheater | 2004-05-04 |
| 6640021 | Fabrication of a hybrid integrated circuit device including an optoelectronic chip | Roy Yu, Chandrika Prasad | 2003-10-28 |
| 6599778 | Chip and wafer integration process using vertical connections | Roy Yu, Chandrika Prasad, Chandrasekhar Narayan | 2003-07-29 |
| 6548325 | Wafer thickness compensation for interchip planarity | — | 2003-04-15 |
| 6460265 | Double-sided wafer exposure method and device | Christopher P. Ausschnitt | 2002-10-08 |
| 6444560 | Process for making fine pitch connections between devices and structure made by the process | Chandrika Prasad, Roy Yu | 2002-09-03 |
| 6429045 | Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Edmund J. Sprogis +1 more | 2002-08-06 |
| 6355501 | Three-dimensional chip stacking assembly | Ka-Hing Fung | 2002-03-12 |
| 6333553 | Wafer thickness compensation for interchip planarity | — | 2001-12-25 |
| 6110806 | Process for precision alignment of chips for mounting on a substrate | — | 2000-08-29 |
| 6087199 | Method for fabricating a very dense chip package | Bijan Davari, Johann Greschner, Howard L. Kalter | 2000-07-11 |
| 6066513 | Process for precise multichip integration and product thereof | Subramania S. Iyer | 2000-05-23 |