Issued Patents All Time
Showing 1–25 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10978143 | Multi-port high performance memory | Xiaoli Hu, Wei Zhao, Igor Arsovski, Yuzheng Jin, Hao Pu +2 more | 2021-04-13 |
| 10522217 | Column-dependent positive voltage boost for memory cell supply voltage | Venkatraghavan Bringivijayaraghavan, Eswararao Potladhurthi | 2019-12-31 |
| 10510384 | Intracycle bitline restore in high performance memory | Venkatraghavan Bringivijayaraghavan | 2019-12-17 |
| 9721628 | Address based memory data path programming scheme | Venkatraghavan Bringivijayaraghavan | 2017-08-01 |
| 9570155 | Circuit to improve SRAM stability | Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan, Arjun Sankar, Sreenivasula Reddy Dhani Reddy | 2017-02-14 |
| 9570156 | Data aware write scheme for SRAM | Venkatraghavan Bringivijayaraghavan, Sheikh Sabiq Chishti | 2017-02-14 |
| 9548104 | Boost control to improve SRAM write operation | Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan, Rahul Nayak | 2017-01-17 |
| 9460811 | Read only memory (ROM) with redundancy | Albert M. Chu, Kevin W. Gorman, Michael R. Ouellette, Ronald A. Piro, Daryl M. Seitzer +2 more | 2016-10-04 |
| 9437282 | High performance sense amplifier | Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan | 2016-09-06 |
| 9390769 | Sense amplifiers and multiplexed latches | Vinay Bhatsoori, Venkatraghavan Bringivijayaraghavan | 2016-07-12 |
| 9236116 | Memory cells with read access schemes | Venkatraghavan Bringivijayaraghavan, Binu Jose, Krishnan S. Rengarajan | 2016-01-12 |
| 8839054 | Read only memory (ROM) with redundancy | Albert M. Chu, Kevin W. Gorman, Michael R. Ouellette, Ronald A. Piro, Daryl M. Seitzer +2 more | 2014-09-16 |
| 8654594 | Vdiff max limiter in SRAMs for improved yield and power | Igor Arsovski, Harold Pilo | 2014-02-18 |
| 8630139 | Dual power supply memory array having a control circuit that dynamically selects a lower of two supply voltages for bitline pre-charge operations and an associated method | Kirk D. Peterson, Harold Pilo | 2014-01-14 |
| 8611164 | Device and method for detecting resistive defect | Harold Pilo, George E. Rudgers | 2013-12-17 |
| 8593861 | Asymmetric memory cells | Krishnan S. Rengarajan | 2013-11-26 |
| 8582351 | Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability | Igor Arsovski, Kevin W. Gorman, Robert M. Houle, Harold Pilo | 2013-11-12 |
| 8279687 | Single supply sub VDD bit-line precharge SRAM and method for level shifting | Chad A. Adams, Daniel Mark Nelson, Harold Pilo, Vinod Ramadurai | 2012-10-02 |
| 8233337 | SRAM delay circuit that tracks bitcell characteristics | Igor Arsovski, Robert M. Houle, Harold Pilo | 2012-07-31 |
| 8233342 | Apparatus and method for implementing write assist for static random access memory arrays | Chad A. Adams, Harold Pilo, Fred J. Towler | 2012-07-31 |
| 7904658 | Structure for power-efficient cache memory | Wagdi W. Abadeer, John A. Fifield, Harold Pilo | 2011-03-08 |
| 7894291 | Circuit and method for controlling a standby voltage level of a memory | John A. Fifield, Harold Pilo | 2011-02-22 |
| 7817481 | Column selectable self-biasing virtual voltages for SRAM write assist | Chad A. Adams, Todd A. Christensen, Harold Pilo | 2010-10-19 |
| 7729159 | Apparatus for improved SRAM device performance through double gate topology | Wilfried Haensch, Joseph A. Iadanza | 2010-06-01 |
| 7643357 | System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture | Steven H. Lamphier, Harold Pilo, Vinod Ramadurai | 2010-01-05 |