Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8669145 | Method and structure for strained FinFET devices | Bruce B. Doris, Huilong Zhu | 2014-03-11 |
| 7741166 | Oxidation method for altering a film structure | Michael P. Belyansky, Bruce B. Doris, Oleg Gluschenkov | 2010-06-22 |
| 7655557 | CMOS silicide metal gate integration | Ricky S. Amos, Cyril Cabral, Jr., Richard D. Kaplan, Jakub Kedzierski, Victor Ku +6 more | 2010-02-02 |
| 7602021 | Method and structure for strained FinFET devices | Bruce B. Doris, Huilong Zhu | 2009-10-13 |
| 7488658 | Stressed semiconductor device structures having granular semiconductor material | Bruce B. Doris, Michael P. Belyansky, Dureseti Chidambarrao, Oleg Gluschenkov | 2009-02-10 |
| 7482243 | Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique | Bruce B. Doris, Meikei Ieong, Devendra K. Sadana | 2009-01-27 |
| 7411227 | CMOS silicide metal gate integration | Ricky S. Amos, Cyril Cabral, Jr., Richard D. Kaplan, Jakub Kedzierski, Victor Ku +6 more | 2008-08-12 |
| 7396747 | Hetero-integrated strained silicon n- and p-MOSFETs | Juan Cai, Kevin K. Chan, Patricia M. Mooney, Kern Rim | 2008-07-08 |
| 7273800 | Hetero-integrated strained silicon n- and p-MOSFETs | Juan Cai, Kevin K. Chan, Patricia M. Mooney, Kern Rim | 2007-09-25 |
| 7250658 | Hybrid planar and FinFET CMOS devices | Bruce B. Doris, Meikei Leong, Thomas S. Kanarsky, Jakub Kedzierski, Min Yang | 2007-07-31 |
| 7247569 | Ultra-thin Si MOSFET device structure and method of manufacture | Bruce B. Doris, Meikei Ieong, Devendra K. Sadana | 2007-07-24 |
| 7202516 | CMOS transistor structure including film having reduced stress by exposure to atomic oxygen | Michael P. Belyansky, Bruce B. Doris, Oleg Gluschenkov | 2007-04-10 |
| 7166521 | SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layer | Hussein I. Hanafi, Erin C. Jones, Dominic J. Schepis, Leathen Shi | 2007-01-23 |
| 7122849 | Stressed semiconductor device structures having granular semiconductor material | Bruce B. Doris, Michael P. Belyansky, Dureseti Chidambarrao, Oleg Gluschenkov | 2006-10-17 |
| 7075150 | Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique | Bruce B. Doris, Meikei Ieong, Devendra K. Sadana | 2006-07-11 |
| 7056782 | CMOS silicide metal gate integration | Ricky S. Amos, Cyril Cabral, Jr., Richard D. Kaplan, Jakub Kedzierski, Victor Ku +6 more | 2006-06-06 |
| 7002214 | Ultra-thin body super-steep retrograde well (SSRW) FET devices | Judson R. Holt, Meikei Ieong, Renee T. Mo, Zhibin Ren, Ghavam G. Shahidi | 2006-02-21 |
| 6982196 | Oxidation method for altering a film structure and CMOS transistor structure formed therewith | Michael P. Belyansky, Bruce B. Doris, Oleg Gluschenkov | 2006-01-03 |
| 6916698 | High performance CMOS device structure with mid-gap metal gate | Anda C. Mocuta, Meikei Ieong, Ricky S. Amos, Dan M. Mocuta, Huajie Chen | 2005-07-12 |
| 6911383 | Hybrid planar and finFET CMOS devices | Bruce B. Doris, Meikei Ieong, Thomas S. Kanarsky, Jakub Kedzierski, Min Yang | 2005-06-28 |
| 6846734 | Method and process to make multiple-threshold metal gates CMOS technology | Ricky S. Amos, Katayun Barmak, Cyril Cabral, Jr., Meikei Leong, Thomas S. Kanarsky +1 more | 2005-01-25 |
| 6841831 | Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process | Hussein I. Hanafi, Kevin K. Chan, Wesley C. Natzle, Leathen Shi | 2005-01-11 |
| 6835633 | SOI wafers with 30-100 å buried oxide (BOX) created by wafer bonding using 30-100 å thin oxide as bonding layer | Hussein I. Hanafi, Erin C. Jones, Dominic J. Schepis, Leathen Shi | 2004-12-28 |
| 6762469 | High performance CMOS device structure with mid-gap metal gate | Anda C. Mocuta, Meikei Ieong, Ricky S. Amos, Dan M. Mocuta, Huajie Chen | 2004-07-13 |
| 6660598 | Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region | Hussein I. Hanafi, Kevin K. Chan, Wesley C. Natzle, Leathen Shi | 2003-12-09 |