DC

David S. Collins

IBM: 31 patents #3,235 of 70,183Top 5%
AM Amgen: 6 patents #564 of 2,867Top 20%
Overall (All Time): #90,000 of 4,157,543Top 3%
37
Patents All Time

Issued Patents All Time

Showing 25 most recent of 37 patents

Patent #TitleCo-InventorsDate
10978452 Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry Phillip F. Chapman, Steven H. Voldman 2021-04-13
10170476 Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry Phillip F. Chapman, Steven H. Voldman 2019-01-01
9842838 Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry Phillip F. Chapman, Steven H. Voldman 2017-12-12
9397010 Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry Phillip F. Chapman, Steven H. Voldman 2016-07-19
9275997 Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry Phillip F. Chapman, Steven H. Voldman 2016-03-01
8853789 Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry Phillip F. Chapman, Steven H. Voldman 2014-10-07
8674423 Semiconductor structure having vias and high density capacitors Kai D. Feng, Zhong-Xiang He, Peter J. Lindgren, Robert M. Rassel 2014-03-18
8420518 Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry Phillip F. Chapman, Steven H. Voldman 2013-04-16
8288244 Lateral passive device having dual annular electrodes Jeffrey B. Johnson, Xuefeng Liu, Bradley A. Orner, Robert M. Rassel, David C. Sheridan 2012-10-16
8288821 SOI (silicon on insulator) substrate improvements Alan B. Botula, Alvin J. Joseph, Howard S. Landis, James A. Slinkman 2012-10-16
8234606 Metal wiring structure for integration with through substrate vias Alvin J. Joseph, Peter J. Lindgren, Anthony K. Stamper, Kimball M. Watson 2012-07-31
8169007 Asymmetric junction field effect transistor Frederick G. Anderson, Richard A. Phelps, Robert M. Rassel, Michael J. Zierak 2012-05-01
8138607 Metal fill structures for reducing parasitic capacitance Howard S. Landis, Anthony K. Stamper, Janet M. Wilson 2012-03-20
8125013 Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors Kai D. Feng, Zhong-Xiang Ile, Peter J. Lindgren, Robert M. Rassel 2012-02-28
8101494 Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors Kai D. Feng, Zhong-Xiang He, Peter J. Lindgren, Robert M. Rassel 2012-01-24
8089126 Method and structures for improving substrate loss and linearity in SOI substrates Alan B. Botula, Alvin J. Joseph, Howard S. Landis, James A. Slinkman, Anthony K. Stamper 2012-01-03
8017471 Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry Phillip F. Chapman, Steven H. Voldman 2011-09-13
8008748 Deep trench varactors Robert M. Rassel, Eric Thompson 2011-08-30
7968975 Metal wiring structure for integration with through substrate vias Alvin J. Joseph, Peter J. Lindgren, Anthony K. Stamper, Kimball M. Watson 2011-06-28
7943445 Asymmetric junction field effect transistor Frederick G. Anderson, Richard A. Phelps, Robert M. Rassel, Michael J. Zierak 2011-05-17
7868423 Optimized device isolation John Benoit, Natalie B. Feilchenfeld, Michael L. Gautsch, Xuefeng Liu, Robert M. Rassel +2 more 2011-01-11
7855420 Structure for a latchup robust array I/O using through wafer via Phillip F. Chapman, Steven H. Voldman 2010-12-21
7821097 Lateral passive device having dual annular electrodes Jeffrey B. Johnson, Xuefeng Liu, Bradley A. Orner, Robert M. Rassel, David C. Sheridan 2010-10-26
7741681 Latchup robust array I/O using through wafer via Phillip F. Chapman, Steven H. Voldman 2010-06-22
7739636 Design structure incorporating semiconductor device structures that shield a bond pad from electrical noise Mete Erturk, Edward J. Gordon, Robert A. Groves, Robert M. Rassel 2010-06-15