Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7979764 | Distributed test compression for integrated circuits | Brian Foutz, Patrick Gallagher, Vivek Chickermane | 2011-07-12 |
| 7478301 | Partial good integrated circuit and method of testing same | Leonard O. Farnsworth, III, Michael Z. Felske, Pamela S. Gillis, Benjamin P. Lynch, Michael R. Ouellette +2 more | 2009-01-13 |
| 7434129 | Partial good integrated circuit and method of testing same | Leonard O. Farnsworth, III, Michael Z. Felske, Pamela S. Gillia, Benjamin P. Lynch, Michael R. Ouellette +2 more | 2008-10-07 |
| 7305600 | Partial good integrated circuit and method of testing same | Leonard O. Farnsworth, III, Michael Z. Felske, Pamela S. Gillis, Benjamin P. Lynch, Michael R. Ouellette +2 more | 2007-12-04 |
| 6804803 | Method for testing integrated logic circuits | Robert W. Bassett, Brion Keller, David E. Lackey, Mark R. Taylor, Donald L. Wheater | 2004-10-12 |
| 6795944 | Testing regularly structured logic circuits in integrated circuit devices | — | 2004-09-21 |
| 6611933 | Real-time decoder for scan test patterns | Bernd Koenemann, Brion Keller | 2003-08-26 |
| 6567943 | D flip-flop structure with flush path for high-speed boundary scan applications | David E. Lackey, Steven F. Oakland | 2003-05-20 |
| 6185710 | High-performance IEEE1149.1-compliant boundary scan cell | — | 2001-02-06 |
| 4205303 | Performing arithmetic using indirect digital-to-analog conversion | — | 1980-05-27 |