Issued Patents All Time
Showing 25 most recent of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12265908 | Methods for increasing cache hit rates for neural networks | Swapnil P. Sakharshete, Ashish Panday | 2025-04-01 |
| 12032487 | Access log and address translation log for a processor | Mark Fowler, Anthony Asaro, Gongxian Jeffrey Cheng, Michael Mantor | 2024-07-09 |
| 11288205 | Access log and address translation log for a processor | Mark Fowler, Anthony Asaro, Gongxian Jeffrey Cheng, Mike Mantor | 2022-03-29 |
| 11100004 | Shared virtual address space for heterogeneous processors | Gongxian Jeffrey Cheng, Mark Fowler, Philip J. Rogers, Anthony Asaro, Mike Mantor +1 more | 2021-08-24 |
| 10467138 | Caching policies for processing units on multiple sockets | Paul Blinzer, Ali Ibrahim, Vydhyanathan Kalyanasundharam | 2019-11-05 |
| 10423354 | Selective data copying between memory modules | Philip J. Rogers, Anthony Asaro, Gongxian Jeffrey Cheng | 2019-09-24 |
| 10255104 | System call queue between visible and invisible computing devices | Michael Clair Houston, Keith Lowery, Newton Cheung | 2019-04-09 |
| 10146575 | Heterogeneous enqueuing and dequeuing mechanism for task scheduling | Michael Clair Houston, Newton Cheung, Keith Lowery | 2018-12-04 |
| 9910788 | Cache access statistics accumulation for cache line replacement selection | Philip J. Rogers, Anthony Asaro | 2018-03-06 |
| 9645854 | Dynamic work partitioning on heterogeneous processing devices | Michael Clair Houston, Newton Cheung, Keith Lowery | 2017-05-09 |
| 9501269 | Automatic source code generation for accelerated function calls | Gregory P. Rodgers, Shreyas Ramalingam | 2016-11-22 |
| 9430281 | Heterogeneous enqueuing and dequeuing mechanism for task scheduling | Michael Clair Houston, Newton Cheung, Keith Lowery | 2016-08-30 |
| 8752064 | Optimizing communication of system call requests | Michael Clair Houston, Newton Cheung, Keith Lowery | 2014-06-10 |
| 8667201 | Computer system interrupt handling | Michael Clair Houston, Newton Cheung, Keith Lowery | 2014-03-04 |
| 8667225 | Store aware prefetching for a datastream | Bharath Narasimha Swamy, Swamy Punyamurtula | 2014-03-04 |
| 8195887 | Processor power management and method | William A. Hughes, Kiran Bondalapati, Vydhyanathan Kalyanasundharam, Kevin M. Lepak | 2012-06-05 |
| 7937569 | System and method for scheduling operations using speculative data operands | Brian D. McMinn | 2011-05-03 |
| 7685406 | Determination of current stack pointer value using architectural and speculative stack pointer delta values | Christopher B. Svec, Faisal A. Syed, Michael E. Tuuk, Gregory W. Smaus | 2010-03-23 |
| 7373484 | Controlling writes to non-renamed register space in an out-of-order execution microprocessor | Arun Radhakrishnan, Michael Filippo, Michael T. Clark, David E. Kroesche | 2008-05-13 |
| 7363470 | System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor | Michael Filippo, James K. Pickett | 2008-04-22 |
| 7315935 | Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots | Mitchell Alsup, Brian D. McMinn, David E. Kroesche | 2008-01-01 |
| 7266673 | Speculation pointers to identify data-speculative operations in microprocessor | Michael Filippo, James K. Pickett | 2007-09-04 |
| 7263600 | System and method for validating a memory file that links speculative results of load operations to register values | Krishnan V. Ramani, Ramsey W. Haddad, Mitchell Alsup | 2007-08-28 |
| 7222226 | System and method for modifying a load operation to include a register-to-register move operation in order to forward speculative load results to a dependent operation | Kevin M. Lepak, James K. Pickett | 2007-05-22 |
| 7197630 | Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation | Mitchell Alsup | 2007-03-27 |