Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11941340 | Cross-hierarchy antenna condition verification | Michael Alexander Bowen, Gerald Strevig, III, Amanda Christine Venton, Robert M. Averill, III, David Wolpert +1 more | 2024-03-26 |
| 11875099 | Noise impact on function (NIOF) reduction for integrated circuit design | Gerald Strevig, III, Alice H. Lee, Jose Luis Pontes Correia Neves | 2024-01-16 |
| 11341311 | Generation and selection of universally routable via mesh specifications in an integrated circuit | Joseph KOONE, Smitha REDDY, Gustavo E. Tellez, Michael Alexander Bowen | 2022-05-24 |
| 11176301 | Noise impact on function (NIOF) reduction for integrated circuit design | Jose L. Neves | 2021-11-16 |
| 11030376 | Net routing for integrated circuit (IC) design | Jose L. Neves | 2021-06-08 |
| 10943040 | Clock gating latch placement | Jesse Peter Surprise, Gerald Strevig, III, Shawn Kollesar | 2021-03-09 |
| 10885243 | Logic partition reporting for integrated circuit design | Jose L. Neves | 2021-01-05 |
| 10878152 | Single-bit latch optimization for integrated circuit (IC) design | Jose L. Neves, Alice H. Lee | 2020-12-29 |
| 10831938 | Parallel power down processing of integrated circuit design | Jose L. Neves | 2020-11-10 |
| 10831953 | Logic partition identifiers for integrated circuit design | Jose L. Neves | 2020-11-10 |
| 10831966 | Multi-fanout latch placement optimization for integrated circuit (IC) design | Jose L. Neves | 2020-11-10 |
| 10360338 | Method for improving capacitance extraction performance by approximating the effect of distant shapes | Susan E. Cellier, Lewis W. Dewey, III, Anthony D. Hagin, Ron D. Rose, David J. Widiger +1 more | 2019-07-23 |
| 10354041 | Process for improving capacitance extraction performance | Robert J. Allen, Susan E. Cellier, Lewis W. Dewey, III, Anthony D. Hagin, Ronald D. Rose +1 more | 2019-07-16 |
| 10331840 | Resource aware method for optimizing wires for slew, slack, or noise | Alice H. Lee, Jose L. Neves | 2019-06-25 |
| 10169526 | Incremental parasitic extraction for coupled timing and power optimization | Kerim Kalafala, Tsz-Mei Ko, Ravichander Ledalla, Alice H. Lee, Jose L. Neves +1 more | 2019-01-01 |
| 10169516 | Methods and computer program products for via capacitance extraction | Susan E. Cellier, Lewis W. Dewey, III, Anthony D. Hagin, Ronald D. Rose, David J. Widiger | 2019-01-01 |
| 9934341 | Simulation of modifications to microprocessor design | Christopher J. Berry, Chris Aaron Cavitt, Jose L. Neves, Jesse Peter Surprise, Michael H. Wood | 2018-04-03 |
| 9928322 | Simulation of modifications to microprocessor design | Christopher J. Berry, Chris Aaron Cavitt, Jose L. Neves, Jesse Peter Surprise, Michael H. Wood | 2018-03-27 |
| 9886541 | Process for improving capacitance extraction performance | Robert J. Allen, Susan E. Cellier, Lewis W. Dewey, III, Anthony D. Hagin, Ronald D. Rose +1 more | 2018-02-06 |
| 9858383 | Incremental parasitic extraction for coupled timing and power optimization | Kerim Kalafala, Tsz-Mei Ko, Ravichander Ledalla, Alice H. Lee, Jose L. Neves +1 more | 2018-01-02 |
| 9785735 | Parallel incremental global routing | Paul M. Campbell, Nathaniel D. Hieter, Douglas Keller, Alexander J. Suess | 2017-10-10 |
| 9256705 | Reducing repeater power | Paul D. Kartschoke, Jose L. Neves | 2016-02-09 |
| 9223918 | Reducing repeater power | Paul D. Kartschoke, Jose L. Neves | 2015-12-29 |
| 8032851 | Structure for an integrated circuit design for reducing coupling between wires of an electronic circuit | Moussadek Belaidi, Markus Buehler, James J. Curtin, Bryan A. Meyer, Douglas S. Search +2 more | 2011-10-04 |
| 8006208 | Reducing coupling between wires of an electronic circuit | Moussadek Belaidi, Markus Buehler, James J. Curtin, Bryan A. Meyer, Douglas S. Search +2 more | 2011-08-23 |