Issued Patents All Time
Showing 26–50 of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8825989 | Technique to perform three-source operations | Avinash Sodani, Alexandre J. Farcy, Per Hammarlund | 2014-09-02 |
| 8782456 | Dynamic and idle power reduction sequence using recombinant clock and power gating | Sin S. Tan, Srikanth Srinivasan, Sivakumar Radhakrishnan, Lily P. Looi | 2014-07-15 |
| 8589663 | Technique to perform three-source operations | Avinash Sodani, Alexandre J. Farcy, Per Hammarlund | 2013-11-19 |
| 8572358 | Meta predictor restoration upon detecting misprediction | Ronny Ronen, Mattan Erez, Adi Yoaz | 2013-10-29 |
| 8510536 | Vector completion mask handling | Michael A. Fetterman, Michael Cornaby, Per Hammarlund, Ronak Signhal, Glenn J. Hinton | 2013-08-13 |
| 8397090 | Operating integrated circuit logic blocks at independent voltages with single voltage supply | Stephen H. Gunther, Edward A. Burton, Anant Deval, Robert Greiner, Mike Cornaby | 2013-03-12 |
| 8291196 | Forward-pass dead instruction identification and removal at run-time | Matthew C. Merten, Alexandre J. Farcy | 2012-10-16 |
| 8285976 | Method and apparatus for predicting branches using a meta predictor | Adi Yoaz, Mattan Erez, Ronny Ronen | 2012-10-09 |
| 8275560 | Power measurement techniques of a system-on-chip (SOC) | Sivakumar Radhakrishnan, Sin S. Tan, Lily P. Looi, Yi-Feng Liu | 2012-09-25 |
| 8239659 | Vector completion mask handling | Michael A. Fetterman, Michael Cornaby, Per Hammarlund, Ronak Signhal, Glenn J. Hinton | 2012-08-07 |
| 8103831 | Efficient method and apparatus for employing a micro-op cache in a processor | Lihu Rappoport, Bob Valentine, Yoav Almog, Franck Sala, Amir Leibovitz +2 more | 2012-01-24 |
| 8069358 | Independent power control of processing cores | Stephen H. Gunther, Edward A. Burton, Anant Deval, Robert Greiner, Michael Cornaby | 2011-11-29 |
| 7949887 | Independent power control of processing cores | Stephen H. Gunther, Edward A. Burton, Anant Deval, Robert Greiner, Michael Cornaby | 2011-05-24 |
| 7913064 | Operation frame filtering, building, and execution | Per Hammarlund, Alexandre J. Farcy, John A. Miller | 2011-03-22 |
| 7797683 | Decoupling the number of logical threads from the number of simultaneous physical threads in a processor | Per Hammarlund, Pierre Michaud, Alexandre J. Farcy, Morris Marden, Robert L. Hinton +1 more | 2010-09-14 |
| 7757065 | Instruction segment recording scheme | Ronny Ronen, Lihu Rappoport | 2010-07-13 |
| 7711898 | Register alias table cache to map a logical register to a physical register | Avinash Sodani, Samie B. Samaan | 2010-05-04 |
| 7644236 | Memory cache bank prediction | Adi Yoaz, Ronny Ronen, Lihu Rappoport, Mattan Erez, Bob Valentine | 2010-01-05 |
| 7562206 | Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions | Avinash Sodani, Alexandre J. Farcy, Per Hammarlund, Mark Charles Davis | 2009-07-14 |
| 7539850 | Enhanced virtual renaming scheme and deadlock prevention therefor | Ronny Ronen, Michael Bekerman | 2009-05-26 |
| 7533247 | Operation frame filtering, building, and execution | Per Hammarlund, Alexandre J. Farcy, John A. Miller | 2009-05-12 |
| 7533252 | Overriding a static prediction with a level-two predictor | Mark Charles Davis, Robert L. Hinton, Boyd Phelps | 2009-05-12 |
| 7529913 | Late allocation of registers | Avinash Sodani, Per Hammarlund | 2009-05-05 |
| 7502912 | Method and apparatus for rescheduling operations in a processor | Avinash Sodani, Per Hammarlund | 2009-03-10 |
| 7475225 | Method and apparatus for microarchitecture partitioning of execution clusters | Avinash Sodani, Alexandre J. Farcy, Per Hammarlund, Sebastien Hily, Mark Charles Davis | 2009-01-06 |