Issued Patents All Time
Showing 51–75 of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7457938 | Staggered execution stack for vector processing | Avinash Sodani, Michael A. Fetterman, Per Hammarlund, Ronak Singhal, Glenn J. Hinton | 2008-11-25 |
| 7457932 | Load mechanism | Per Hammarlund, Michael A. Fetterman, Glenn J. Hinton, Sebastien Hily, Ronak Singhal | 2008-11-25 |
| 7454596 | Method and apparatus for partitioned pipelined fetching of multiple execution threads | Robert L. Hinton | 2008-11-18 |
| 7444457 | Retrieving data blocks with reduced linear addresses | Chris Yunker, Pierre Michaud | 2008-10-28 |
| 7428627 | Method and apparatus for predicting values in a processor having a plurality of prediction modes | Michael Bekerman, Ronny Ronen, Lihu Rappoport | 2008-09-23 |
| 7404065 | Flow optimization and prediction for VSSE memory operations | Per Hammarlund, Michael A. Fetterman, Michael Cornaby, Glenn J. Hinton, Avinash Sodani | 2008-07-22 |
| 7398372 | Fusing load and alu operations | Nicholas Samra, David J. Sager, Glenn J. Hinton | 2008-07-08 |
| 7349284 | Memory array with staged output | Boyd Phelps, Chris E. Yuker | 2008-03-25 |
| 7284116 | Method and system for safe data dependency collapsing based on control-flow speculation | Freddy Gabbay, Ronny Ronen, Adi Yoaz | 2007-10-16 |
| 7260704 | Method and apparatus for reinforcing a prefetch chain | Robert N. Cooksey | 2007-08-21 |
| 7243219 | Predicting instruction branches with a plurality of global predictors using varying amounts of history instruction | Mark Charles Davis, Pierre Michaud | 2007-07-10 |
| 7203825 | Sharing information to reduce redundancy in hybrid branch prediction | Herbert Hum | 2007-04-10 |
| 7181597 | Decoding instructions for trace cache resume state in system passing decoded operations to both trace cache and execution allocation module | John A. Miller | 2007-02-20 |
| 7181598 | Prediction of load-store dependencies in a processing agent | Darrell D. Boggs, John A. Miller, Ronak Singhal | 2007-02-20 |
| 7155599 | Method and apparatus for a register renaming structure | Michael Bekerman, Ronny Ronen | 2006-12-26 |
| 7143273 | Method and apparatus for dynamic branch prediction utilizing multiple stew algorithms for indexing a global history | John A. Miller, Slade Morgan | 2006-11-28 |
| 7136992 | Method and apparatus for a stew-based loop predictor | Subramaniam Maiyuran, Peter J. Smith | 2006-11-14 |
| 7130965 | Apparatus and method for store address for store address prefetch and line locking | Per Hammarlund, Sebastien Hily, Aravindh Baktha, Hermann W. Gartler | 2006-10-31 |
| 7093077 | Method and apparatus for next-line prefetching from a predicted memory address | Robert N. Cooksey | 2006-08-15 |
| 7080236 | Updating stack pointer based on instruction bit indicator without executing an update microinstruction | Alan B. Kyker, Nicholas Samra | 2006-07-18 |
| 7062640 | Instruction segment filtering scheme | Alan Miller, Glenn J. Hinton | 2006-06-13 |
| 7017026 | Generating lookahead tracked register value based on arithmetic operation indication | Adi Yoaz, Ronny Ronen, Michael Bekerman | 2006-03-21 |
| 7002873 | Memory array with staged output | Boyd Phelps, Chris E. Yuker | 2006-02-21 |
| 6990551 | System and method for employing a process identifier to minimize aliasing in a linear-addressed cache | Herbert Hum, Per Hammarlund | 2006-01-24 |
| 6954840 | Method and apparatus for content-aware prefetching | Robert N. Cooksey | 2005-10-11 |