Issued Patents All Time
Showing 26–48 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7084495 | Electroosmotic pumps using porous frits for cooling integrated circuit stacks | R. Scott List, James G. Maveety, Alan M. Myers, Quat Vu | 2006-08-01 |
| 7063938 | Method of preparing patterned colloidal crystals | Seung-Man Yang, Ki-Ra Yi, Yong-Hak Park | 2006-06-20 |
| 7056807 | Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack | Scot Kellar, R. Scott List | 2006-06-06 |
| 7056813 | Methods of forming backside connections on a wafer stack | Patrick Morrow, R. Scott List | 2006-06-06 |
| 7037804 | Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration | Scot Kellar, R. Scott List | 2006-05-02 |
| 7034394 | Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same | Shriram Ramanathan, R. Scott List, Gregory M. Chrysler | 2006-04-25 |
| 6992381 | Using external radiators with electroosmotic pumps for cooling integrated circuits | R. Scott List, James G. Maveety, Alan M. Myers, Quat Vu, Ravi Prasher +2 more | 2006-01-31 |
| 6981849 | Electro-osmotic pumps and micro-channels | R. Scott List, James G. Maveety, Alan M. Myers, Quat Vu, Ravi Prasher +1 more | 2006-01-03 |
| 6977435 | Thick metal layer integrated process flow to improve power delivery and mechanical buffering | Bob Martell, Dave Ayers, R. Scott List, Peter K. Moon, Steven Towle | 2005-12-20 |
| 6975016 | Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof | Scot Kellar, R. Scott List | 2005-12-13 |
| 6943440 | Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow | Kevin J. Lee, Steven Towle | 2005-09-13 |
| 6914002 | Differential planarization | James A. Boardman, Paul B. Fischer, Mauro J. Kobrinsky | 2005-07-05 |
| 6911373 | Ultra-high capacitance device based on nanostructures | Scot Kellar | 2005-06-28 |
| 6908565 | Etch thinning techniques for wafer-to-wafer vertical stacks | R. Scott List | 2005-06-21 |
| 6897125 | Methods of forming backside connections on a wafer stack | Patrick Morrow, R. Scott List | 2005-05-24 |
| 6887769 | Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same | Scot Kellar, R. Scott List | 2005-05-03 |
| 6870270 | Method and structure for interfacing electronic devices | Mauro J. Kobrinsky, R. Scott List, Michael C. Harmes | 2005-03-22 |
| 6790748 | Thinning techniques for wafer-to-wafer vertical stacks | R. Scott List, Mauro J. Kobrinsky | 2004-09-14 |
| 6790780 | Fabrication of 3-D capacitor with dual damascene process | R. Scott List, Bruce A. Block | 2004-09-14 |
| 6762076 | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices | R. Scott List, Scot Kellar | 2004-07-13 |
| 6661085 | Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack | Scot Kellar, R. Scott List | 2003-12-09 |
| 6645832 | Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack | R. Scott List, Tom Letson | 2003-11-11 |
| 6599808 | Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode | Scot Kellar | 2003-07-29 |