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USPTO Patent Rankings Data through Dec 31, 2025
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Scot Kellar — 15 Patents

Intel: 15 patents #2,763 of 30,777Top 9%
Bend, OR: #65 of 663 inventorsTop 10%
Oregon: #2,909 of 28,073 inventorsTop 15%
Overall (All Time): #307,048 of 4,157,543Top 8%
15 Patents All Time
Scot Kellar has been granted 15 US patents while listed as an inventor at Intel. The first was granted in 2003 and the most recent in March 2025. Scot Kellar ranks #307,048 of 4,157,543 US inventors in our database (top 7.4%). Patent records list Scot Kellar in Bend, OR, US.

Issued Patents All Time

Showing 1–15 of 15 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12242315 Thermal management in horizontally or vertically stacked dies Somvir Dahiya, Stephen H. Gunther, Julien Sebot, Randy B. Osborne, Joshua Een 2025-03-04
10068866 Integrated circuit package having rectangular aspect ratio Darren Crews 2018-09-04 $19,235,000
7271434 Capacitor with insulating nanostructure Sarah Kim 2007-09-18 $14,997,000
7265406 Capacitor with conducting nanostructure Sarah Kim 2007-09-04 $18,654,000
7244983 Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode Sarah Kim 2007-07-17 $13,694,000
7157787 Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices Sarah Kim, R. Scott List 2007-01-02
7091084 Ultra-high capacitance device based on nanostructures Sarah Kim 2006-08-15 $13,533,000
7056807 Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack Sarah Kim, R. Scott List 2006-06-06 $10,284,000
7037804 Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration Sarah Kim, R. Scott List 2006-05-02 $12,289,000
6975016 Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof Sarah Kim, R. Scott List 2005-12-13 $11,810,000
6911373 Ultra-high capacitance device based on nanostructures Sarah Kim 2005-06-28 $36,074,000
6887769 Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same Sarah Kim, R. Scott List 2005-05-03 $20,343,000
6762076 Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices Sarah Kim, R. Scott List 2004-07-13 $47,892,000
6661085 Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack Sarah Kim, R. Scott List 2003-12-09 $40,688,000
6599808 Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode Sarah Kim 2003-07-29 $49,479,000