Issued Patents All Time
Showing 76–100 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9418035 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Fulvio Spagna, Ashish Gupta | 2016-08-16 |
| 9418009 | Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory | Adrian C. Moga, Vedaraman Geetha, Bahaa Fahim, Yen-Cheng Liu, Jeffrey D. Chamberlain +1 more | 2016-08-16 |
| 9405687 | Method, apparatus and system for handling cache misses in a processor | Bahaa Fahim, Samuel D. Strom, Vedaraman Geetha, Yen-Cheng Liu, Krishnakumar Ganapathy +1 more | 2016-08-02 |
| 9355058 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Fulvio Spagna, Debendra Das Sharma, Jeffrey C. Swanson | 2016-05-31 |
| 9336175 | Utilization-aware low-overhead link-width modulation for power reduction in interconnects | Ankush Varma, Buck Gremel, Krishnakanth V. Sistla, Michael Cole | 2016-05-10 |
| 9280507 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Jeff Willey | 2016-03-08 |
| 9235520 | Protocol for conflicting memory transactions | Manoj K. Arora, Rahul Pal, Dheemanth Nagaraj | 2016-01-12 |
| 9229897 | Embedded control channel for high speed serial interconnect | Venkatraman Iyer, Debendra Das Sharma, Darren S. Jue | 2016-01-05 |
| 9208121 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Fulvio Spagna, Debendra Das Sharma, Jeffrey C. Swanson | 2015-12-08 |
| 9208110 | Raw memory transaction support | Robert J. Safranek, Zhong-Ning Cai | 2015-12-08 |
| 9183171 | Fast deskew when exiting low-power partial-width high speed link state | Venkatraman Iyer, Debendra Das Sharma, Darren S. Jue | 2015-11-10 |
| 9098415 | PCI express transaction descriptor | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2015-08-04 |
| 9053244 | Utilization-aware low-overhead link-width modulation for power reduction in interconnects | Ankush Varma, Buck Gremel, Krishnakanth V. Sistla, Michael Cole | 2015-06-09 |
| 9032103 | Transaction re-ordering | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2015-05-12 |
| 9026682 | Prefectching in PCI express | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2015-05-05 |
| 8984228 | Providing common caching agent for core and integrated input/output (IO) module | Yen-Cheng Liu, Geeyarpuram N. Santhanakrishnan, Ganapati Srinivasa, Kenneth C. Creta, Sridhar Muthrasanallur +1 more | 2015-03-17 |
| 8868955 | Enhanced interconnect link width modulation for power savings | Venkatraman Iyer, Dennis R. Halicki | 2014-10-21 |
| 8793404 | Atomic operations | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2014-07-29 |
| 8717882 | Repurposing data lane as clock lane by migrating to reduced speed link operation | Venkatraman Iyer, Allen J. Baum | 2014-05-06 |
| 8555101 | PCI express enhancements and extensions | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2013-10-08 |
| 8549183 | PCI express enhancements and extensions | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2013-10-01 |
| 8473642 | PCI express enhancements and extensions including device window caching | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2013-06-25 |
| 8447888 | PCI express enhancements and extensions | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2013-05-21 |
| 8347018 | Techniques for broadcasting messages on a point-to-point interconnect | Keshavan Tiruvallur, Kenneth C. Creta | 2013-01-01 |
| 8250435 | Memory error detection and/or correction | Dennis W. Brzezinski, Edwin F. Mendez Valverde | 2012-08-21 |