Issued Patents All Time
Showing 51–75 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10073775 | Apparatus and method for triggered prefetching to improve I/O and producer-consumer workload efficiency | Christopher B. Wilerkson, Ren Wang, Antoine Kaufmann, Anil Vasudevan, Venkata Krishnan +1 more | 2018-09-11 |
| 10061719 | Packed write completions | Brian S. Morris, Jeffrey C. Swanson, Bill Nale, Jeff Willey, Eric L. Hendrickson | 2018-08-28 |
| 9916266 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Fulvio Spagna, Ashish Gupta | 2018-03-13 |
| 9910807 | Ring protocol for low latency interconnect switch | Geeyarpuram N. Santhanakrishnan, Yen-Cheng Liu, Bahaa Fahim, Ganapati Srinivasa | 2018-03-06 |
| 9898408 | Sharing aware snoop filter apparatus and method | Samantika S. Sury, Simon C. Steely, Jr. | 2018-02-20 |
| 9753885 | Multislot link layer flit wherein flit includes three or more slots whereby each slot comprises respective control field and respective payload field | Jeff Willey, Jeffrey C. Swanson, Robert J. Safranek | 2017-09-05 |
| 9740654 | Control messaging in multislot link layer flit | Jeff Willey, Jeffrey C. Swanson | 2017-08-22 |
| 9740646 | Early identification in transactional buffered memory | Brian S. Morris, Bill Nale, Jeffrey C. Swanson | 2017-08-22 |
| 9729309 | Securing data transmission between processor packages | Simon P. Johnson, Abhishek Das, Carlos V. Rozas, Uday Savagaonkar, Kiran Padwekar | 2017-08-08 |
| 9697158 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Jeff Willey | 2017-07-04 |
| 9658963 | Speculative reads in buffered memory | Brian S. Morris, Bill Nale, Yen-Cheng Liu | 2017-05-23 |
| 9639276 | Implied directory state updates | — | 2017-05-02 |
| 9639490 | Ring protocol for low latency interconnect switch | Geeyarpuram N. Santhanakrishnan, Yen-Cheng Liu, Bahaa Fahim, Ganapati Srinivasa | 2017-05-02 |
| 9632862 | Error handling in transactional buffered memory | Brian S. Morris, Bill Nale, Eric L. Hendrickson | 2017-04-25 |
| 9626321 | High performance interconnect | Robert J. Safranek, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue +18 more | 2017-04-18 |
| 9619396 | Two level memory full line writes | Jeffrey D. Chamberlain, Yen-Cheng Liu, Vedaraman Geetha | 2017-04-11 |
| 9575895 | Providing common caching agent for core and integrated input/output (IO) module | Yen-Cheng Liu, Geeyarpuram N. Santhanakrishnan, Ganapati Srinivasa, Kenneth C. Creta, Sridhar Muthrasanallur +1 more | 2017-02-21 |
| 9552253 | Probabilistic flit error checking | Venkatraman Iyer, Debendra Das Sharma | 2017-01-24 |
| 9535838 | Atomic operations in PCI express | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2017-01-03 |
| 9507746 | Control messaging in multislot link layer flit | Jeff Willey, Jeffrey C. Swanson | 2016-11-29 |
| 9479196 | High performance interconnect link layer | Jeff Willey, Jeffrey C. Swanson, Robert J. Safranek | 2016-10-25 |
| 9442879 | Multiple transaction data flow control unit for high-speed interconnect | Robert J. Safranek, Debendra Das Sharma | 2016-09-13 |
| 9444492 | High performance interconnect link layer | Jeff Willey, Jeffrey C. Swanson, Robert J. Safranek | 2016-09-13 |
| 9442855 | Transaction layer packet formatting | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2016-09-13 |
| 9436605 | Cache coherency apparatus and method minimizing memory writeback operations | Jeffrey D. Chamberlain, Vedaraman Geetha, Yen-Cheng Liu, Adrian C. Moga, Herbert Hum +1 more | 2016-09-06 |