Issued Patents All Time
Showing 51–75 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8171321 | Method and apparatus for cost and power efficient, scalable operating system independent services | Arvind Kumar, Glenn J. Hinton, Johan G. Van De Groenendaal | 2012-05-01 |
| 8078831 | Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors | Hong Wang, Perry Wang, Jeffery A. Brown, George Z. Chrysos, Doron Orenstein +2 more | 2011-12-13 |
| 8074274 | User-level privilege management | Hong Wang, Gautham Chinya, Perry Wang, Jamison D. Collins, Richard Hankins +1 more | 2011-12-06 |
| 8019947 | Technique for thread communication and synchronization | Quinn A. Jacobson, Hong Wang, John Shen | 2011-09-13 |
| 7991965 | Technique for using memory attributes | Quinn A. Jacobson, Anne W. Bracy, Hong Wang, John Shen, Matthew C. Merten +6 more | 2011-08-02 |
| 7913064 | Operation frame filtering, building, and execution | Stephan Jourdan, Alexandre J. Farcy, John A. Miller | 2011-03-22 |
| 7882339 | Primitives to enhance thread-level speculation | Quinn A. Jacobson, Hong Wang, John Shen, Gautham Chinya, Xiang Zou +2 more | 2011-02-01 |
| 7849465 | Programmable event driven yield mechanism which may activate service threads | Xiang Zou, Hong Wang, Scott Dion Rodgers, Darrell D. Boggs, Bryant Bigbee +8 more | 2010-12-07 |
| 7844801 | Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors | Hong Wang, Perry Wang, Jeffery A. Brown, George Z. Chrysos, Doron Orenstein +2 more | 2010-11-30 |
| 7818547 | Method and apparatus for efficient resource utilization for prescient instruction prefetch | Tor M. Aamodt, Hong Wang, John Shen, Steve Shih-wei Liao, Perry Wang | 2010-10-19 |
| 7814469 | Speculative multi-threading for instruction prefetch and/or trace pre-build | Hong Wang, Tor M. Aamodt, Pedro Marcuello, Jared W. Stark, IV, John Shen +4 more | 2010-10-12 |
| 7797683 | Decoupling the number of logical threads from the number of simultaneous physical threads in a processor | Stephan Jourdan, Pierre Michaud, Alexandre J. Farcy, Morris Marden, Robert L. Hinton +1 more | 2010-09-14 |
| 7757045 | Synchronizing recency information in an inclusive cache hierarchy | Christopher Shannon, Ronak Singhal, Hermann W. Gartler, Glenn J. Hinton | 2010-07-13 |
| 7743233 | Sequencer address management | Hong Wang, Gautham Chinya, Richard Hankins, Shivnandan Kaushik, Bryant Bigbee +13 more | 2010-06-22 |
| 7730281 | System and method for storing immediate data | Alan B. Kyker, Chan Woo Lee, Robert F. Krick, Hitesh Ahuja, William C. Alexander +1 more | 2010-06-01 |
| 7688746 | Method and system for dynamic resource allocation | Melih Ozgul | 2010-03-30 |
| 7657880 | Safe store for speculative helper threads | Hong Wang, Tor M. Aamodt, John Shen, Xinmin Tian, Milind B. Girkar +2 more | 2010-02-02 |
| 7640419 | Method for and a trailing store buffer for use in memory renaming | Sebastien Hily | 2009-12-29 |
| 7640384 | Queued locks using monitor-memory wait | James B. Crossland, Anil Aggarwal, Shivnandan Kaushik | 2009-12-29 |
| 7603527 | Resolving false dependencies of speculative load instructions | Sebastien Hily, Zhongying Zhang | 2009-10-13 |
| 7587584 | Mechanism to exploit synchronization overhead to improve multithreaded performance | Natalie D. Enright, Jamison D. Collins, Perry Wang, Hong Wang, Xinmin Tran +2 more | 2009-09-08 |
| 7562206 | Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions | Avinash Sodani, Alexandre J. Farcy, Stephan Jourdan, Mark Charles Davis | 2009-07-14 |
| 7533247 | Operation frame filtering, building, and execution | Stephan Jourdan, Alexandre J. Farcy, John A. Miller | 2009-05-12 |
| 7529913 | Late allocation of registers | Avinash Sodani, Stephan Jourdan | 2009-05-05 |
| 7529914 | Method and apparatus for speculative execution of uncontended lock instructions | Bratin Saha, Matthew C. Merten | 2009-05-05 |