Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7627735 | Implementing vector memory operations | Roger Espasa, Geoff Lowney, Roger Gramunt, Santiago Galan, Toni Juan +3 more | 2009-12-01 |
| 7558920 | Apparatus and method for partitioning a shared cache of a chip multi-processor | Matthew Mattina, Antonio Juan-Hormigo, Ramon Matas-Navarro | 2009-07-07 |
| 7555703 | Method and apparatus for reducing false error detection in a microprocessor | Shubhendu Sekhar Mukherjee, Steven K. Reinhardt, Christopher T. Weaver, Michael J. Smith | 2009-06-30 |
| 7543221 | Method and apparatus for reducing false error detection in a redundant multi-threaded system | Shubhendu Sekhar Mukherjee, Steven K. Reinhardt, Christopher T. Weaver, Michael J. Smith | 2009-06-02 |
| 7475321 | Detecting errors in directory entries | Sudhanva Gurumurthi, Arijit Biswas, Shubhendu Sekhar Mukherjee | 2009-01-06 |
| 7444497 | Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support | Steven K. Reinhardt, Shubhendu Sekhar Mukherjee, Christopher T. Weaver | 2008-10-28 |
| 7404070 | Branch prediction combining static and dynamic prediction techniques | Harish Patil, Stephen Felix | 2008-07-22 |
| 7386756 | Reducing false error detection in a microprocessor by tracking instructions neutral to errors | Shubhendu Sekhar Mukherjee, Steven K. Reinhardt, Christopher T. Weaver | 2008-06-10 |
| 7373548 | Hardware recovery in a multi-threaded architecture | Steven K. Reinhardt, Shubhendu Sekhar Mukherjee | 2008-05-13 |
| 7353365 | Implementing check instructions in each thread within a redundant multithreading environments | Shubhendu Sekhar Mukherjee, Steven K. Reinhardt, Christopher T. Weaver | 2008-04-01 |
| 7343602 | Software controlled pre-execution in a multithreaded processor | Chi-Keung Luk | 2008-03-11 |
| 7308607 | Periodic checkpointing in a redundantly multi-threaded architecture | Steven K. Reinhardt, Shubhendu Sekhar Mukherjee | 2007-12-11 |
| 7243262 | Incremental checkpointing in a multi-threaded architecture | Shubhendu Sekhar Mukherjee, Steven K. Reinhardt | 2007-07-10 |
| 7003648 | Flexible demand-based resource allocation for multiple requestors in a simultaneous multi-threaded CPU | George Z. Chrysos, Chuan-Hua Chang, John H. Mylius, Peter G. Soderquist | 2006-02-21 |
| 6704861 | Mechanism for executing computer instructions in parallel | Francis X. McKeen, Michael C. Adler, Robert P. Nix, David J. Sager, P. Geoffrey Lowney | 2004-03-09 |
| 6675192 | Temporary halting of thread execution until monitoring of armed events to memory location identified in working registers | Rebecca L. Stamm, Bruce E. Edwards, Matthew Reilly, Craig B. Zilles, Tryggve Fossum +2 more | 2004-01-06 |
| 6493741 | Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit | Rebecca L. Stamm, Bruce E. Edwards, Matthew Reilly, Craig B. Zilles, Tryggve Fossum +2 more | 2002-12-10 |
| 6470443 | Pipelined multi-thread processor selecting thread instruction in inter-stage buffer based on count information | Rebecca L. Stamm, Trggve Fossum, Robert H. Halstead, Jr., George Z. Chrysos, Dean Tullsen +2 more | 2002-10-22 |
| 6449713 | Implementation of a conditional move instruction in an out-of-order processor | Bruce E. Edwards, Daniel Leibholz, Edward J. McLellan, Derrick R. Meyer | 2002-09-10 |
| 6154828 | Method and apparatus for employing a cycle bit parallel executing instructions | Joseph Macri, Francis X. McKeen, William R. Grundmann, Robert P. Nix, David A. Webb | 2000-11-28 |
| 6108770 | Method and apparatus for predicting memory dependence using store sets | George Z. Chrysos, Bruce E. Edwards, John H. Edmondson | 2000-08-22 |
| 6081887 | System for passing an index value with each prediction in forward direction to enable truth predictor to associate truth value with particular branch instruction | Simon C. Steely, Jr., Edward J. McLellan | 2000-06-27 |
| 6073159 | Thread properties attribute vector based thread selection in multithreading processor | Rebecca L. Stamm, Trggve Fossum, Robert H. Halstead, Jr., George Z. Chrysos, Dean Tullsen +2 more | 2000-06-06 |
| 5933860 | Multiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predicted | Simon C. Steely, Jr., Edward J. McLellan | 1999-08-03 |
| 5758142 | Trainable apparatus for predicting instruction outcomes in pipelined processors | Scott McFarling, Simon C. Steely, Jr., Edward J. McLellan | 1998-05-26 |