Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7294879 | Vertical MOSFET with dual work function materials | Xiangdong Chen, Geng Wang, Qiqing C. Ouyang | 2007-11-13 |
| 7129564 | Structure and method of forming a notched gate field effect transistor | Jochen Beintner, Naim Moumen, Porshia Wrschka | 2006-10-31 |
| 7018551 | Pull-back method of forming fins in FinFets | Jochen Beintner, Dureseti Chidambarrao, Kenneth T. Settlemyer, Jr. | 2006-03-28 |
| 7015552 | Dual work function semiconductor structure with borderless contact and method of fabricating the same | Qiuyi Ye, William R. Tonti | 2006-03-21 |
| 6964892 | N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same | Lawrence A. Clevenger, Rama Divakaruni, Louis L. Hsu | 2005-11-15 |
| 6930004 | Self-aligned drain/channel junction in vertical pass transistor DRAM cell design for device scaling | Geng Wang, Kevin McStay, Mary E. Weybright, Dureseti Chidambarrao | 2005-08-16 |
| 6908815 | Dual work function semiconductor structure with borderless contact and method of fabricating the same | Qiuyi Ye, William R. Tonti | 2005-06-21 |
| 6905976 | Structure and method of forming a notched gate field effect transistor | Jochen Beintner, Naim Moumen, Porshia Wrschka | 2005-06-14 |
| 6642584 | Dual work function semiconductor structure with borderless contact and method of fabricating the same | Qiuyi Ye, William R. Tonti | 2003-11-04 |
| 6528855 | MOSFET having a low aspect ratio between the gate and the source/drain | Qiuyi Ye, William R. Tonti, Jack A. Mandelman | 2003-03-04 |
| 6444548 | Bitline diffusion with halo for improved array threshold voltage control | Ramachandra Divakaruni, Jack A. Mandelman | 2002-09-03 |
| 6433397 | N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same | Lawrence A. Clevenger, Rama Divakaruni, Louis L. Hsu | 2002-08-13 |
| 6387782 | Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer | Hiroyuki Akatsu, Omer H. Dokumaci, Suryanarayan G. Hegde, Rajesh Rengarajan, Paul A. Ronsheim | 2002-05-14 |
| 6348394 | Method and device for array threshold voltage control by trapped charge in trench isolation | Jack A. Mandelman, Rama Divakaruni, Herbert L. Ho, Giuseppe La Rosa, Jochen Beintner +1 more | 2002-02-19 |
| 6329271 | Self-aligned channel implantation | Hiroyuki Akatsu, Jochen Beintner | 2001-12-11 |
| 6329704 | Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer | Hiroyuki Akatsu, Omer H. Dokumaci, Suryanarayan G. Hegde, Rajesh Rengarajan, Paul A. Ronsheim | 2001-12-11 |
| 6297530 | Self aligned channel implantation | Hiroyuki Akatsu, Jochen Beintner | 2001-10-02 |