Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9082877 | Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor | Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha +1 more | 2015-07-14 |
| 9040399 | Threshold voltage adjustment for thin body MOSFETs | MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha +3 more | 2015-05-26 |
| 8993389 | Dummy gate interconnect for semiconductor device | Brian J. Greene, Xiaojun Yu | 2015-03-31 |
| 8976344 | Live optical fiber identifier tool | Ryuji Takaoka | 2015-03-10 |
| 8962417 | Method and structure for pFET junction profile with SiGe channel | Kern Rim, William K. Henson, Xinlin Wang | 2015-02-24 |
| 8853035 | Tucked active region without dummy poly for performance boost and variation reduction | Xiaojun Yu, Brian J. Greene | 2014-10-07 |
| 8835234 | MOS having a sic/sige alloy stack | Dureseti Chidambarrao, Brian J. Greene, Xiaojun Yu | 2014-09-16 |
| 8803243 | Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor | Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha +1 more | 2014-08-12 |
| 8785291 | Post-gate shallow trench isolation structure formation | Xiaojun Yu, Brian J. Greene | 2014-07-22 |
| 8779469 | Post-gate shallow trench isolation structure formation | Brian J. Greene, Xiaojun Yu | 2014-07-15 |
| 8766378 | Programmable FETs using Vt-shift effect and methods of manufacture | Eduard A. Cartier, Qingqing Liang, Yanfeng Wang | 2014-07-01 |
| 8729637 | Work function adjustment by carbon implant in semiconductor devices including gate structure | Dechao Guo, William K. Henson, Shreesh Narasimha, Yanfeng Wang | 2014-05-20 |
| 8659054 | Method and structure for pFET junction profile with SiGe channel | Kern Rim, William K. Henson, Xinlin Wang | 2014-02-25 |
| 8629022 | Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same | Dureseti Chidambarrao, Sunfei Fang, Xiaojun Yu, Jun Yuan | 2014-01-14 |
| 8492247 | Programmable FETs using Vt-shift effect and methods of manufacture | Eduard A. Cartier, Qingqing Liang, Yanfeng Wang | 2013-07-23 |
| 8476706 | CMOS having a SiC/SiGe alloy stack | Dureseti Chidambarrao, Brian J. Greene, Xiaojun Yu | 2013-07-02 |
| 8466496 | Selective partial gate stack for improved device isolation | Xiaojun Yu, Dureseti Chidambarrao, Brian J. Greene | 2013-06-18 |
| 8445974 | Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same | Dureseti Chidambarrao, Sunfei Fang, Xiaojun Yu, Jun Yuan | 2013-05-21 |
| 8436427 | Dual metal and dual dielectric integration for metal high-K FETs | Michael P. Chudzik, Wiliam K. Henson, Rashmi Jha, Ravikumar Ramachandran, Richard S. Wise | 2013-05-07 |
| 8354309 | Method of providing threshold voltage adjustment through gate dielectric stack modification | Brian J. Greene, Michael P. Chudzik, Shu-Jen Han, William K. Henson, Edward P. Maciejewski +3 more | 2013-01-15 |
| 8227870 | Method and structure for gate height scaling with high-k/metal gate technology | Michael P. Chudzik, Ricardo A. Donaton, William K. Henson | 2012-07-24 |
| 8138037 | Method and structure for gate height scaling with high-k/metal gate technology | Michael P. Chudzik, Ricardo A. Donaton, William K. Henson | 2012-03-20 |
| 8106455 | Threshold voltage adjustment through gate dielectric stack modification | Brian J. Greene, Michael P. Chudzik, Shu-Jen Han, William K. Henson, Edward P. Maciejewski +3 more | 2012-01-31 |
| 7999332 | Asymmetric semiconductor devices and method of fabricating | Jun Yuan, Dureseti Chidambarrao, Sunfei Fang, Haizhou Yin, Xiaojun Yu | 2011-08-16 |
| 7943457 | Dual metal and dual dielectric integration for metal high-k FETs | Michael P. Chudzik, Wiliam K. Henson, Rashmi Jha, Ravikumar Ramachandran, Richard S. Wise | 2011-05-17 |