Issued Patents All Time
Showing 126–150 of 323 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10615256 | Nanosheet transistor gate structure having reduced parasitic capacitance | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2020-04-07 |
| 10608109 | Vertical transistor with enhanced drive current | Kangguo Cheng, Alexander Reznicek | 2020-03-31 |
| 10608083 | Non-planar field effect transistor devices with low-resistance metallic gate structures | Kangguo Cheng, Chen Zhang, Wenyu Xu | 2020-03-31 |
| 10607894 | Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2020-03-31 |
| 10607892 | Junction formation in thick-oxide and thin-oxide vertical FETs on the same chip | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2020-03-31 |
| 10600886 | Vertical field effect transistors with bottom source/drain epitaxy | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2020-03-24 |
| 10593753 | Vertical field effect transistor (VFET) device with controllable top spacer | Wenyu Xu, Chen Zhang, Kangguo Cheng | 2020-03-17 |
| 10593673 | Nanosheet with single epitaxial stack forming off-set dual material channels for gate-all-around CMOS | Jingyun Zhang, Alexander Reznicek, Choonghyun Lee | 2020-03-17 |
| 10593598 | Vertical FET with various gate lengths by an oxidation process | Kangguo Cheng, Chen Zhang | 2020-03-17 |
| 10592698 | Analog-based multiple-bit chip security | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2020-03-17 |
| 10580855 | High thermal budget compatible punch through stop integration using doped glass | Kangguo Cheng, Sanjay C. Mehta, Chun-Chen Yeh | 2020-03-03 |
| 10580854 | High thermal budget compatible punch through stop integration using doped glass | Kangguo Cheng, Sanjay C. Mehta, Chun-Chen Yeh | 2020-03-03 |
| 10580770 | Vertical transistors with different gate lengths | Chen Zhang, Kangguo Cheng, Juntao Li | 2020-03-03 |
| 10580709 | Flipped vertical field-effect-transistor | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2020-03-03 |
| 10573714 | Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs | Josephine B. Chang, Michael A. Guillorn, Isaac Lauer | 2020-02-25 |
| 10566445 | Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates | Zhenxing Bi, Kangguo Cheng, Nicolas Loubet, Wenyu Xu, Chen Zhang | 2020-02-18 |
| 10566444 | Vertical fin field effect transistor with a reduced gate-to-bottom source/drain parasitic capacitance | Chen Zhang, Kangguo Cheng, Wenyu Xu | 2020-02-18 |
| 10566240 | Wimpy device by selective laser annealing | Kangguo Cheng, Nicolas Loubet, Alexander Reznicek | 2020-02-18 |
| 10559692 | Nanosheet substrate isolation scheme by lattice matched wide bandgap semiconductor | Alexander Reznicek, Jingyun Zhang, Choonghyun Lee | 2020-02-11 |
| 10559504 | High mobility semiconductor fins on insulator | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2020-02-11 |
| 10559502 | Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2020-02-11 |
| 10553493 | Fabrication of a vertical transistor with self-aligned bottom source/drain | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2020-02-04 |
| 10553445 | Stacked nanowires | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2020-02-04 |
| 10541335 | Stress induction in 3D device channel using elastic relaxation of high stress material | Kangguo Cheng, Nicolas Loubet, Alexander Reznicek | 2020-01-21 |
| 10541330 | Forming stacked nanowire semiconductor device | Kangguo Cheng, Peng Xu, Chen Zhang | 2020-01-21 |