Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9244851 | Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index | Ekaterina M. Ambroladze, Michael A. Blake, Garrett M. Drapala, Pak-kin Mak, Arthur J. O'Neill | 2016-01-26 |
| 9003127 | Storing data in a system memory for a subsequent cache flush | Michael A. Blake, Hieu T. Huynh, Kenneth D. Klapproth, Pak-kin Mak, Vesselina K. Papazova | 2015-04-07 |
| 8990507 | Storing data in a system memory for a subsequent cache flush | Michael A. Blake, Pak-kin Mak, Hieu T. Huynh, Kenneth D. Klapproth, Vesselina K. Papazova | 2015-03-24 |
| 8972664 | Multilevel cache hierarchy for finding a cache line on a remote node | Garrett M. Drapala, Michael A. Blake, Craig R. Walters, Pak-kin Mak | 2015-03-03 |
| 8930616 | System refresh in cache memory | Michael A. Blake, Hieu T. Huynh, Kenneth D. Klapproth | 2015-01-06 |
| 8918587 | Multilevel cache hierarchy for finding a cache line on a remote node | Garrett M. Drapala, Michael A. Blake, Craig R. Walters, Pak-kin Mak | 2014-12-23 |
| 8874957 | Dynamic cache correction mechanism to allow constant access to addressable index | Ekaterina M. Ambroladze, Michael A. Blake, Hieu T. Huynh | 2014-10-28 |
| 8719618 | Dynamic cache correction mechanism to allow constant access to addressable index | Ekaterina M. Ambroladze, Michael A. Blake, Hieu T. Huynh | 2014-05-06 |
| 8688880 | Centralized serialization of requests in a multiprocessor system | Garrett M. Drapala, Michael A. Blake, Lawrence D. Curley | 2014-04-01 |
| 8560891 | EDRAM macro disablement in cache memory | Michael A. Blake, Hieu T. Huynh, Pak-kin Mak | 2013-10-15 |
| 8560767 | Optimizing EDRAM refresh rates in a high performance cache architecture | Michael Fee, Arthur J. O'Neill, Scott Barnett Swaney | 2013-10-15 |
| 8458405 | Cache bank modeling with variable access and busy times | Garrett M. Drapala, Hieu T. Huynh, Kenneth D. Klapproth | 2013-06-04 |
| 8381019 | EDRAM macro disablement in cache memory | Michael A. Blake, Hieu T. Huynh, Pak-kin Mak | 2013-02-19 |
| 8291157 | Concurrent refresh in cache memory | Hieu T. Huynh, Charlie C. Hwang, Kenneth D. Klapproth | 2012-10-16 |
| 8244972 | Optimizing EDRAM refresh rates in a high performance cache architecture | Michael Fee, Arthur J. O'Neill, Scott Barnett Swaney | 2012-08-14 |
| 7702972 | Method and apparatus for SRAM macro sparing in computer chips | Garrett M. Drapala, Hieu T. Huynh, Patrick J. Meaney | 2010-04-20 |
| 6985990 | System and method for implementing private devices on a secondary peripheral component interface | John M. Sheplock, Phillip G. Williams | 2006-01-10 |
| 6973528 | Data caching on bridge following disconnect | Glenn D. Gilda, John M. Sheplock, Phillip G. Williams | 2005-12-06 |
| 6968415 | Opaque memory region for I/O adapter transparent bridge | Stefan P. Jackowski, John M. Sheplock, Phillip G. Williams | 2005-11-22 |
| 6920519 | System and method for supporting access to multiple I/O hub nodes in a host bridge | Bruce Beukema, Ronald Edward Fuhs, Glenn D. Gilda, Anthony J. Bybell, Stefan P. Jackowski +2 more | 2005-07-19 |
| 6785759 | System and method for sharing I/O address translation caching across multiple host bridges | Bruce Beukema, Ronald Edward Fuhs, Glenn D. Gilda | 2004-08-31 |
| 6621353 | Phase locked loop reconfiguration | David Andrew Thorndike | 2003-09-16 |
| 6442634 | System and method for interrupt command queuing and ordering | Wai Ling Lee, Vincent P. Zeyak, Jr. | 2002-08-27 |
| 6279064 | System and method for loading commands to a bus, directly loading selective commands while queuing and strictly ordering other commands | Wai Ling Lee, Vincent P. Zeyak, Jr. | 2001-08-21 |
| 6182237 | System and method for detecting phase errors in asics with multiple clock frequencies | Bruce George Rudolph | 2001-01-30 |