Issued Patents All Time
Showing 76–100 of 220 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7865862 | Design structure for dynamically selecting compiled instructions | Deanna J. Chou, Jesse E. Craig, John Sargis, Jr., Daneyand J. Singley | 2011-01-04 |
| 7831935 | Method and architecture for power management of an electronic device | Kerry Bernstein, Kenneth J. Goodnow, Clarence R. Ogilvie, Keith R. Williams | 2010-11-09 |
| 7823002 | Digital reliability monitor having autonomic repair and notification capability | Anthony R. Bonaccio, Michael LeStrange, William R. Tonti | 2010-10-26 |
| 7823107 | Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design | Igor Arsovski, Serafino Bueti, Joseph A. Iadanza, Jason M. Norman, Hemen R. Shah | 2010-10-26 |
| 7821294 | Integrated circuit containing multi-state restore circuitry for restoring state to a power-managed functional block | Susan K. Lichtensteiger, Michael R. Ouellette, Raymond Schuppe | 2010-10-26 |
| 7793251 | Method for increasing the manufacturing yield of programmable logic devices | Kenneth J. Goodnow, Clarence R. Ogilvie, Christopher B. Reynolds, Paul S. Zuchowski | 2010-09-07 |
| 7791968 | Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator | Kerry Bernstein, Kenneth J. Goodnow, Clarence R. Ogilvie, Keith R. Williams | 2010-09-07 |
| 7773159 | Switching system for signal monitoring and switch-back control | Ahmed Y. Ginawi, Casey J. Grant, Christopher Ro | 2010-08-10 |
| 7770139 | Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path | Igor Arsovski, Anthony R. Bonaccio, Hayden C. Cranford, Jr., Joseph A. Iadanza, Pradeep Thiagarajan | 2010-08-03 |
| 7765351 | High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips | Pascal A. Nsame, Anthony D. Polson, Nancy H. Pratt | 2010-07-27 |
| 7761690 | Method, apparatus and computer program product for dynamically selecting compiled instructions | Deanna J. Chou, Jesse E. Craig, John Sargis, Jr., Daneyand J. Singley | 2010-07-20 |
| 7755420 | Intrinsic RC power distribution for noise filtering of analog supplies | Anthony R. Bonaccio, Hayden C. Cranford, Jr., Joseph A. Iadanza, Stephen D. Wyatt | 2010-07-13 |
| 7752355 | Asynchronous packet based dual port link list header and data credit management structure | Emory D. Keller, Anthony J. Perri | 2010-07-06 |
| 7750670 | System and method for dynamically executing a function in a programmable logic array | Kenneth J. Goodnow, Clarence R. Ogilvie, Christopher B. Reynolds, Jack R. Smith | 2010-07-06 |
| 7743270 | Assigning clock arrival time for noise reduction | Igor Arsovski, Joseph A. Iadanza, Jason M. Norman | 2010-06-22 |
| 7732949 | System for method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly | Kenneth J. Goodnow, Clarence R. Ogilvie, Keith R. Williams | 2010-06-08 |
| 7716007 | Design structures of powering on integrated circuit | Igor Arsovski, Anthony R. Bonaccio, Serafino Bueti, Hayden C. Cranford, Jr., Joseph A. Iadanza +3 more | 2010-05-11 |
| 7715995 | Design structure for measurement of power consumption within an integrated circuit | Kenneth J. Goodnow, Clarence R. Ogilvie, Nitin Sharma, Charles S. Woodruff | 2010-05-11 |
| 7644327 | System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA | John M. Cohn, Christopher B. Reynolds, Paul S. Zuchowski | 2010-01-05 |
| 7643591 | Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design | Igor Arsovski, Serafino Bueti, Joseph A. Iadanza, Jason M. Norman, Hemen R. Shah | 2010-01-05 |
| 7633819 | Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator | Kerry Bernstein, Kenneth J. Goodnow, Clarence R. Ogilvie, Keith R. Williams | 2009-12-15 |
| 7536496 | Method and apparatus for transmitting data in an integrated circuit | W. Riyon Harding, David W. Milton, Clarence R. Ogilvie, Jason Rotella, Paul M. Schanely | 2009-05-19 |
| 7511548 | Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees | Serafino Bueti, Hayden C. Cranford, Jr., Joseph A. Iadanza, Pradeep Thiagarajan | 2009-03-31 |
| 7495492 | Dynamic latch state saving device and protocol | Pascal A. Nsame, Anthony J. Perri, Lansing U. Pickup, Matthew R. Walland | 2009-02-24 |
| 7489163 | FPGA powerup to known functional state | Kenneth J. Goodnow, Clarence R. Ogilvie, Christopher B. Reynolds, Jack R. Smith, Keith R. Williams | 2009-02-10 |