Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8539404 | Functional simulation redundancy reduction by state comparison and pruning | Jason M. Norman | 2013-09-17 |
| 8484481 | Chip lockout protection scheme for integrated circuit devices and insertion thereof | Stanley B. Stanski, Scott T. Vento | 2013-07-09 |
| 8103998 | Verifying non-deterministic behavior of a design under test | Suzanne Granato, Francis A. Kampf, Barbara L. Powers | 2012-01-24 |
| 7865862 | Design structure for dynamically selecting compiled instructions | Deanna J. Chou, John Sargis, Jr., Daneyand J. Singley, Sebastian T. Ventrone | 2011-01-04 |
| 7761690 | Method, apparatus and computer program product for dynamically selecting compiled instructions | Deanna J. Chou, John Sargis, Jr., Daneyand J. Singley, Sebastian T. Ventrone | 2010-07-20 |
| 7710683 | Multi-arm disk drive system having interleaved read/write operations and method of controlling same | Stanley B. Stanski, Scott T. Vento | 2010-05-04 |
| 7385781 | Multi-arm disk drive system having interleaved read/write operations and method of controlling same | Stanley B. Stanski, Scott T. Vento | 2008-06-10 |
| 7360138 | Verification of the design of an integrated circuit background | Suzanne Granato, Francis A. Kampf, Barbara L. Powers | 2008-04-15 |
| 7308663 | Circuit design verification using checkpointing | Jason M. Norman | 2007-12-11 |