Issued Patents All Time
Showing 26–50 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9959382 | Adaptive characterization and instantiation of timing abstracts | Eric A. Foreman, Jeffrey G. Hemmett, Dileep N. Netrabile, Stephen G. Shuma, Natesan Venkateswaran +1 more | 2018-05-01 |
| 9922149 | Integration of functional analysis and common path pessimism removal in static timing analysis | Peter C. Elmendorf, Stephen G. Shuma, Alexander J. Suess | 2018-03-20 |
| 9916405 | Distributed timing analysis of a partitioned integrated circuit design | Tsung-Wei Huang, Debjit Sinha, Natesan Venkateswaran | 2018-03-13 |
| 9910954 | Programmable clock division methodology with in-context frequency checking | Naiju K. Abdul, Jennifer E. Basile, Hemlata Gupta, Jeremy J. Leitzen, Stephen G. Shuma +3 more | 2018-03-06 |
| 9864824 | System and method for efficient statistical timing analysis of cycle time independent tests | David J. Hathaway, Stephen G. Shuma, Chandramouli Visweswariah | 2018-01-09 |
| 9858383 | Incremental parasitic extraction for coupled timing and power optimization | Tsz-Mei Ko, Ravichander Ledalla, Alice H. Lee, Adam P. Matheny, Jose L. Neves +1 more | 2018-01-02 |
| 9853866 | Efficient parallel processing of a network with conflict constraints between nodes | Hemlata Gupta, David J. Hathaway, Ronald D. Rose | 2017-12-26 |
| 9852246 | System and method for efficient statistical timing analysis of cycle time independent tests | David J. Hathaway, Stephen G. Shuma, Chandramouli Visweswariah | 2017-12-26 |
| 9836572 | Incremental common path pessimism analysis | Tsung-Wei Huang, Vasant Rao, Debjit Sinha, Natesan Venkateswaran | 2017-12-05 |
| 9798850 | System and method for combined path tracing in static timing analysis | Peter C. Elmendorf, Prabhat Maurya | 2017-10-24 |
| 9785737 | Parallel multi-threaded common path pessimism removal in multiple paths | David J. Hathaway, Vasant Rao, Alexander J. Suess, Vladimir Zolotov | 2017-10-10 |
| 9767239 | Timing optimization driven by statistical sensitivites | Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Gregory M. Schaeffer, Stephen G. Shuma +3 more | 2017-09-19 |
| 9754062 | Timing adjustments across transparent latches to facilitate power reduction | Gregory M. Schaeffer, Stephen G. Shuma, Paul G. Villarrubia | 2017-09-05 |
| 9710594 | Variation-aware timing analysis using waveform construction | SheshaShayee K. Raghunathan, Debjit Sinha, Michael H. Wood, Vladimir Zolotov | 2017-07-18 |
| 9646122 | Variable accuracy parameter modeling in statistical timing | Eric A. Foreman, Jeffrey G. Hemmett, Gregory M. Schaeffer, Stephen G. Shuma, Alexander J. Suess +2 more | 2017-05-09 |
| 9639654 | Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuit | Bijian Chen, David J. Hathaway, Nathaniel D. Hieter, Jeffrey S. Piaget, Alexander J. Suess | 2017-05-02 |
| 9607124 | Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints | Adil Bhanji, Ravichander Ledalla, Debjit Sinha, Chandramouli Visweswariah, Michael H. Wood | 2017-03-28 |
| 9608868 | Efficient parallel processing of a network with conflict constraints between nodes | Hemlata Gupta, David J. Hathaway, Ronald D. Rose | 2017-03-28 |
| 9600617 | Automated timing analysis | Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov | 2017-03-21 |
| 9594868 | Scaling voltages in relation to die location | Eric A. Foreman, Nazmul Habib | 2017-03-14 |
| 9569571 | Method and system for timing violations in a circuit | Jeanne P. Bickford, Eric A. Foreman, Sudeep Mandal, Shashank B. Sreekanta | 2017-02-14 |
| 9542524 | Static timing analysis (STA) using derived boundary timing constraints for out-of-context (OOC) hierarchical entity analysis and abstraction | James C. Gregerson, David J. Hathaway, Tsz-Mei Ko, Alex Rubin | 2017-01-10 |
| 9519747 | Dynamic and adaptive timing sensitivity during static timing analysis using look-up table | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway +6 more | 2016-12-13 |
| 9501609 | Selection of corners and/or margins using statistical static timing analysis of an integrated circuit | Eric A. Foreman, Jeffrey G. Hemmett, Gregory M. Schaeffer, Stephen G. Shurma, Alexander J. Suess +3 more | 2016-11-22 |
| 9495218 | Efficient parallel processing of a network with conflict constraints between nodes | Hemlata Gupta, David J. Hathaway, Ronald D. Rose | 2016-11-15 |