Issued Patents All Time
Showing 201–225 of 548 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10840145 | Vertical field-effect transistor devices with non-uniform thickness bottom spacers | Kangguo Cheng, Choonghyun Lee, Shogo Mochizuki | 2020-11-17 |
| 10840147 | Fin cut forming single and double diffusion breaks | Junli Wang, Kangguo Cheng, Ruilong Xie | 2020-11-17 |
| 10840148 | One-time programmable device compatible with vertical transistor processing | Kangguo Cheng, Ruilong Xie, Chanro Park | 2020-11-17 |
| 10833191 | Integrating nanosheet transistors, on-chip embedded memory, and extended-gate transistors on the same substrate | Julien Frougier, Ruilong Xie, Kangguo Cheng | 2020-11-10 |
| 10833200 | Techniques for forming vertical transport FET having gate stacks with a combination of work function metals | Choonghyun Lee, Kangguo Cheng | 2020-11-10 |
| 10833157 | iFinFET | Kangguo Cheng, Chen Zhang, Xin Miao | 2020-11-10 |
| 10833165 | Asymmetric air spacer gate-controlled device with reduced parasitic capacitance | Kangguo Cheng, Son V. Nguyen, Chanro Park | 2020-11-10 |
| 10832947 | Fully aligned via formation without metal recessing | Chanro Park, Ruilong Xie, Kangguo Cheng | 2020-11-10 |
| 10832970 | Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor | Choonghyun Lee, Kangguo Cheng, Peng Xu | 2020-11-10 |
| 10833073 | Vertical transistors with different gate lengths | Xin Miao, Chen Zhang, Kangguo Cheng | 2020-11-10 |
| 10818756 | Vertical transport FET having multiple threshold voltages with zero-thickness variation of work function metal | Choonghyun Lee, Kangguo Cheng, Shogo Mochizuki | 2020-10-27 |
| 10804262 | Cointegration of FET devices with decoupling capacitor | Kangguo Cheng, Yi Song | 2020-10-13 |
| 10804166 | Porous silicon relaxation medium for dislocation free CMOS devices | Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Devendra K. Sadana | 2020-10-13 |
| 10788446 | Ion-sensitive field-effect transistor with micro-pillar well to enhance sensitivity | Kangguo Cheng, Ruilong Xie, Chanro Park | 2020-09-29 |
| 10790379 | Vertical field effect transistor with anchor | Ruilong Xie, Kangguo Cheng | 2020-09-29 |
| 10777647 | Fin-type FET with low source or drain contact resistance | Kangguo Cheng, Heng Wu, Peng Xu | 2020-09-15 |
| 10777658 | Method and structure of fabricating I-shaped silicon vertical field-effect transistors | Choonghyun Lee, Kangguo Cheng, Peng Xu | 2020-09-15 |
| 10770454 | On-chip metal-insulator-metal (MIM) capacitor and methods and systems for forming same | Chanro Park, Ruilong Xie, Kangguo Cheng | 2020-09-08 |
| 10770562 | Interlayer dielectric replacement techniques with protection for source/drain contacts | Kangguo Cheng, Andrew M. Greene, Vimal Kamineni, Adra Carr, Chanro Park +1 more | 2020-09-08 |
| 10770546 | High density nanotubes and nanotube devices | Choonghyun Lee, Kangguo Cheng, Peng Xu | 2020-09-08 |
| 10763118 | Cyclic selective deposition for tight pitch patterning | Kangguo Cheng, Zhenxing Bi, Dexin Kong | 2020-09-01 |
| 10756170 | VFET devices with improved performance | Kangguo Cheng, Choonghyun Lee, Shogo Mochizuki | 2020-08-25 |
| 10756175 | Inner spacer formation and contact resistance reduction in nanosheet transistors | Choonghyun Lee, Kangguo Cheng, Shogo Mochizuki | 2020-08-25 |
| 10756088 | Method and structure of forming strained channels for CMOS device fabrication | Kangguo Cheng, John G. Gaudiello | 2020-08-25 |
| 10746691 | Ion-sensitive field effect transistor (ISFET) with enhanced sensitivity | Kangguo Cheng, Chanro Park, Ruilong Xie | 2020-08-18 |