Issued Patents All Time
Showing 51–75 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10545875 | Tag accelerator for low latency DRAM cache | Kevin M. Lepak, Ganesh Balakrishnan, Ravindra N. Bhargava | 2020-01-28 |
| 10540316 | Cancel and replay protocol scheme to improve ordered bandwidth | Eric Christopher Morton, Chen-Ping Yang, Amit P. Apte, Elizabeth M. Cooper | 2020-01-21 |
| 10503648 | Cache to cache data transfer acceleration techniques | Amit P. Apte, Ganesh Balakrishnan, Ann Ling, Ravindra N. Bhargava | 2019-12-10 |
| 10491524 | Load balancing scheme | Alan Dodson Smith, Chintan S. Patel, Eric Christopher Morton, Narendra Kamat | 2019-11-26 |
| 10467138 | Caching policies for processing units on multiple sockets | Paul Blinzer, Ali Ibrahim, Benjamin T. Sander | 2019-11-05 |
| 10366008 | Tag and data organization in large memory caches | Ganesh Balakrishnan, Kevin M. Lepak | 2019-07-30 |
| 10305509 | Compression of frequent data values across narrow links | Greggory D. Donley, Bryan P. Broussard | 2019-05-28 |
| 10248564 | Contended lock request elision scheme | Eric Christopher Morton, Amit P. Apte, Elizabeth M. Cooper | 2019-04-02 |
| 10223280 | Input/output memory map unit and northbridge | Yaniv Adiri, Philip Ng, Maggie Chan, Vincent Cueva, Anthony Asaro +4 more | 2019-03-05 |
| 10042576 | Method and apparatus for compressing addresses | Greggory D. Donley | 2018-08-07 |
| 10025721 | Input/output memory map unit and northbridge | Philip Ng, Maggie Chan, Vincent Cueva, Anthony Asaro, Jimshed Mirza +4 more | 2018-07-17 |
| 9793919 | Compression of frequent data values across narrow links | Greggory D. Donley, Bryan P. Broussard | 2017-10-17 |
| 9697146 | Resource management for northbridge using tokens | Douglas R. Williams, Marius Evers, Michael K. Fertig | 2017-07-04 |
| 9507715 | Coherency probe with link or domain indicator | Eric Christopher Morton, Patrick Conway, Elizabeth M. Cooper | 2016-11-29 |
| 9354970 | Method and apparatus for encoding erroneous data in an error correction code protected memory | Ross V. La Fetra, Vilas Sridharan, Dean A. Liberty, Amit P. Apte | 2016-05-31 |
| 9141541 | Nested channel address interleaving | Kevin M. Brandl, Adnan Dhanani | 2015-09-22 |
| 8996816 | Method and apparatus for selectively bypassing a cache for trace collection in a processor | Greggory D. Donley, Benjamin Tsien, Patrick Conway, William A. Hughes | 2015-03-31 |
| 8732410 | Method and apparatus for accelerated shared data migration | Kevin M. Lepak, William A. Hughes, Benjamin Tsien, Greggory D. Donley | 2014-05-20 |
| 8195887 | Processor power management and method | William A. Hughes, Kiran Bondalapati, Kevin M. Lepak, Benjamin T. Sander | 2012-06-05 |
| 7996653 | Shared resources in a chip multiprocessor | William A. Hughes, Kiran Bondalapati, Philip E. Madrid, Stephen C. Ennis | 2011-08-09 |
| 7882327 | Communicating between partitions in a statically partitioned multiprocessing system | William A. Hughes, Patrick Conway, Jeffrey Dwork | 2011-02-01 |
| 7877558 | Memory controller prioritization scheme | William A. Hughes, Philip E. Madrid, Roger D. Isaac | 2011-01-25 |
| 7840780 | Shared resources in a chip multiprocessor | William A. Hughes, Kiran Bondalapati, Philip E. Madrid, Stephen C. Ennis | 2010-11-23 |
| 7383423 | Shared resources in a chip multiprocessor | William A. Hughes, Kiran Bondalapati, Philip E. Madrid, Stephen C. Ennis | 2008-06-03 |
| 7328371 | Core redundancy in a chip multiprocessor for highly reliable systems | William A. Hughes, Philip E. Madrid, Scott White, Ajay Naini | 2008-02-05 |