Issued Patents All Time
Showing 76–78 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7165132 | Processing node including a plurality of processor cores and an interconnect configurable in a test-mode to cause first and second transaction source indicators to be interchanged | Creigton S. Asato, Kevin J. McGrath, William A. Hughes | 2007-01-16 |
| 6549997 | Dynamic variable page size translation of addresses | — | 2003-04-15 |
| 6542423 | Read port design and method for register array | Ajay Naini | 2003-04-01 |