| 7165132 |
Processing node including a plurality of processor cores and an interconnect configurable in a test-mode to cause first and second transaction source indicators to be interchanged |
Kevin J. McGrath, William A. Hughes, Vydhyanathan Kalyanasundharam |
2007-01-16 |
| 6289442 |
Circuit and method for tagging and invalidating speculatively executed instructions |
— |
2001-09-11 |
| 6157995 |
Circuit and method for reducing data dependencies between instructions |
— |
2000-12-05 |
| 5886541 |
Combined logic gate and latch |
— |
1999-03-23 |
| 5541528 |
CMOS buffer circuit having increased speed |
Robert K. Montoye, John J. Zasio, Tarang Patil |
1996-07-30 |
| 5297069 |
Finite impulse response filter |
Christoph Ditzen |
1994-03-22 |
| 5291457 |
Sequentially accessible non-volatile circuit for storing data |
Christoph Ditzen, James A. Rowson |
1994-03-01 |
| 5212782 |
Automated method of inserting pipeline stages in a data path element to achieve a specified operating frequency |
Suresh K. B. Dholakia, Christoph Ditzen |
1993-05-18 |
