Issued Patents All Time
Showing 51–75 of 104 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6255169 | Process for fabricating a high-endurance non-volatile memory device | Xiao-Yu Li, Qi Xiang | 2001-07-03 |
| 6232223 | High integrity borderless vias with protective sidewall spacer | Khanh Tran | 2001-05-15 |
| 6232221 | Borderless vias | Khanh Tran, Andre Stolmeijer | 2001-05-15 |
| 6232631 | Floating gate memory cell structure with programming mechanism outside the read path | Christopher O. Schmidt | 2001-05-15 |
| 6221733 | Reduction of mechanical stress in shallow trench isolation process | Xiao-Yu Li, Robert H. Tu | 2001-04-24 |
| 6215700 | PMOS avalanche programmed floating gate memory cell structure | Steven J. Fong, Stewart Logie | 2001-04-10 |
| 6214666 | Method of forming a non-volatile memory device | — | 2001-04-10 |
| 6211022 | Field leakage by using a thin layer of nitride deposited by chemical vapor deposition | Jonathan Lin, Radu Barsan | 2001-04-03 |
| 6208559 | Method of operating EEPROM memory cells having transistors with thin gate oxide and reduced disturb | Robert H. Tu | 2001-03-27 |
| 6207989 | Non-volatile memory device having a high-reliability composite insulation layer | Xiao-Yu Li | 2001-03-27 |
| 6197638 | Oxide formation process for manufacturing programmable logic device | — | 2001-03-06 |
| 6190966 | Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration | Minh Van Ngo | 2001-02-20 |
| 6184105 | Method for post transistor isolation | Yowjuang W. Liu | 2001-02-06 |
| 6172392 | Boron doped silicon capacitor plate | Christopher O. Schmidt, Xiao-Yu Li | 2001-01-09 |
| 6166428 | Formation of a barrier layer for tungsten damascene interconnects by nitrogen implantation of amorphous silicon or polysilicon | William G. En, Darin A. Chan, Raymond T. Lee | 2000-12-26 |
| 6097090 | High integrity vias | Khanh Tran, Andre Stolmeijer | 2000-08-01 |
| 6093946 | EEPROM cell with field-edgeless tunnel window using shallow trench isolation process | Xiao-Yu Li | 2000-07-25 |
| 6087696 | Stacked tunneling dielectric technology for improving data retention of EEPROM cell | Xiao-Yu Li, Qi Xiang | 2000-07-11 |
| 6087275 | Reduction of n-channel parasitic transistor leakage by using low power/low pressure phosphosilicate glass | Minh Van Ngo, Nicholas R. Maccrae | 2000-07-11 |
| 6075724 | Method for sorting semiconductor devices having a plurality of non-volatile memory cells | Xiao-Yu Li | 2000-06-13 |
| 6075293 | Semiconductor device having a multi-layer metal interconnect structure | Xiao-Yu Li, Van-Hung Pham, Amit P. Marathe | 2000-06-13 |
| 6071784 | Annealing of silicon oxynitride and silicon nitride films to eliminate high temperature charge loss | Radu Barsan | 2000-06-06 |
| 6064595 | Floating gate memory apparatus and method for selected programming thereof | Stewart Logie, Steven J. Fong | 2000-05-16 |
| 6064105 | Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide | Xiao-Yu Li, Radu Barsan | 2000-05-16 |
| 6060766 | Protection of hydrogen sensitive regions in semiconductor devices from the positive charge associated with plasma deposited barriers or layers | William G. En | 2000-05-09 |