Issued Patents All Time
Showing 76–100 of 104 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6040019 | Method of selectively annealing damaged doped regions | Emi Ishida, Xiao-Yu Li | 2000-03-21 |
| 6034893 | Non-volatile memory cell having dual avalanche injection elements | — | 2000-03-07 |
| 6028789 | Zero-power CMOS non-volatile memory cell having an avalanche injection element | Brad Sharpe-Geisler, Steven J. Fong | 2000-02-22 |
| 6025637 | Spacer-based antifuse structure for low capacitance and high reliability and method of fabrication thereof | — | 2000-02-15 |
| 6009033 | Method of programming and erasing an EEPROM device under an elevated temperature and apparatus thereof | Xiao-Yu Li | 1999-12-28 |
| 5999449 | Two transistor EEPROM cell using P-well for tunneling across a channel | Xiao-Yu Li | 1999-12-07 |
| 5989957 | Process for fabricating semiconductor memory device with high data retention including silicon oxynitride etch stop layer formed at high temperature with low hydrogen ion concentration | Minh Van Ngo, David K. Foote | 1999-11-23 |
| 5982035 | High integrity borderless vias with protective sidewall spacer | Khanh Tran | 1999-11-09 |
| 5969992 | EEPROM cell using P-well for tunneling across a channel | Xiao-Yu Li | 1999-10-19 |
| 5960274 | Oxide formation process for manufacturing programmable logic device | — | 1999-09-28 |
| 5956610 | Method and system for providing electrical insulation for local interconnect in a logic circuit | William G. En, Fei Wang, Stewart Logie | 1999-09-21 |
| 5942780 | Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate | Radu Barsan, Xiao-Yu Li | 1999-08-24 |
| 5940735 | Reduction of charge loss in nonvolatile memory cells by phosphorus implantation into PECVD nitride/oxynitride films | Che-Hoo Ng | 1999-08-17 |
| 5925932 | Borderless vias | Khanh Tran, Andre Stolmeijer | 1999-07-20 |
| 5908308 | Use of borophosphorous tetraethyl orthosilicate (BPTEOS) to improve isolation in a transistor array | Radu Barsan, Jonathan Lin | 1999-06-01 |
| 5904575 | Method and apparatus incorporating nitrogen selectively for differential oxide growth | Emi Ishida, Xiao-Yu Li | 1999-05-18 |
| 5885904 | Method to incorporate, and a device having, oxide enhancement dopants using gas immersion laser doping (GILD) for selectively growing an oxide layer | Emi Ishida, Xiao-Yu Li | 1999-03-23 |
| 5854114 | Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide | Xiao-Yu Li, Radu Barsan | 1998-12-29 |
| 5841701 | Method of charging and discharging floating gage transistors to reduce leakage current | Xiao-Yu Li, Radu Barsan | 1998-11-24 |
| 5830795 | Simplified masking process for programmable logic device manufacture | Radu Barsan | 1998-11-03 |
| 5795627 | Method for annealing damaged semiconductor regions allowing for enhanced oxide growth | Emi Ishida, Xiao-Yu Li | 1998-08-18 |
| 5789269 | Field implant for semiconductor device | Jonathan Lin | 1998-08-04 |
| 5756367 | Method of making a spacer based antifuse structure for low capacitance and high reliability | — | 1998-05-26 |
| 5679599 | Isolation using self-aligned trench formation and conventional LOCOS | — | 1997-10-21 |
| 5672521 | Method of forming multiple gate oxide thicknesses on a wafer substrate | Radu Barsan, Xiao-Yu Li | 1997-09-30 |