Issued Patents All Time
Showing 26–50 of 104 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6600188 | EEPROM with a neutralized doping at tunnel window edge | Chun Jiang | 2003-07-29 |
| 6596587 | Shallow junction EEPROM device and process for fabricating the device | — | 2003-07-22 |
| 6577007 | Manufacturing process for borderless vias with respect to underlying metal | — | 2003-06-10 |
| 6570212 | Complementary avalanche injection EEPROM cell | Steven J. Fong, Stewart Logie | 2003-05-27 |
| 6545313 | EEPROM tunnel window for program injection via P+ contacted inversion | Chun Jiang, Robert H. Tu | 2003-04-08 |
| 6524911 | Combination of BPTEOS oxide film with CMP and RTA to achieve good data retention | — | 2003-02-25 |
| 6515899 | Non-volatile memory cell with enhanced cell drive current | Robert H. Tu | 2003-02-04 |
| 6489806 | Zero-power logic cell for use in programmable logic devices | Fabiano Fontana | 2002-12-03 |
| 6472308 | Borderless vias on bottom metal | — | 2002-10-29 |
| 6455375 | Eeprom tunnel window for program injection via P+ contacted inversion | Chun Jiang, Robert H. Tu | 2002-09-24 |
| 6455593 | Method of dynamic retardation of cell cycle kinetics to potentiate cell damage | Philip M. Grimley | 2002-09-24 |
| 6455912 | Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress | Hyeon-Seag Kim | 2002-09-24 |
| 6424003 | EEPROM cell with self-aligned tunneling window | Xiao-Yu Li, Christopher O. Schmidt | 2002-07-23 |
| 6424000 | Floating gate memory apparatus and method for selected programming thereof | — | 2002-07-23 |
| 6362527 | Borderless vias on bottom metal | — | 2002-03-26 |
| 6326663 | Avalanche injection EEPROM memory cell with P-type control gate | Xiao-Yu Li, Steven J. Fong | 2001-12-04 |
| 6309942 | STI punch-through defects and stress reduction by high temperature oxide reflow process | Ting Tsui, Robert H. Tu, Xiao-Yu Li | 2001-10-30 |
| 6303949 | Method and system for providing electrical insulation for local interconnect in a logic circuit | William G. En, Fei Wang, Stewart Logie | 2001-10-16 |
| 6297128 | Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress | Hyeon-Seag Kim | 2001-10-02 |
| 6291327 | Optimization of S/D annealing to minimize S/D shorts in memory array | Xiao-Yu Li, Christopher O. Schmidt, Robert H. Tu | 2001-09-18 |
| 6287916 | Method for forming a semiconductor device using LPCVD nitride to protect floating gate from charge loss | — | 2001-09-11 |
| 6282123 | Method of fabricating, programming, and erasing a dual pocket two sided program/erase non-volatile memory cell | — | 2001-08-28 |
| 6274576 | Method of dynamic retardation of cell cycle kinetics to potentiate cell damage | Philip M. Grimley | 2001-08-14 |
| 6274898 | Triple-well EEPROM cell using P-well for tunneling across a channel | Xiao-Yu Li | 2001-08-14 |
| 6261944 | Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect | Xiao-Yu Li | 2001-07-17 |