Issued Patents All Time
Showing 101–125 of 127 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6121150 | Sputter-resistant hardmask for damascene trench/via formation | Fei Wang | 2000-09-19 |
| 6117781 | Optimized trench/via profile for damascene processing | Todd P. Lukanc, Fei Wang | 2000-09-12 |
| 6117782 | Optimized trench/via profile for damascene filling | Todd P. Lukanc, Fei Wang | 2000-09-12 |
| 6074949 | Method of preventing copper dendrite formation and growth | Diana M. Schonauer, Kai Yang | 2000-06-13 |
| 6051882 | Subtractive dual damascene semiconductor device | Subhash Gupta, Rich Klein, Scott Luning, Ming-Rin Lin | 2000-04-18 |
| 6048802 | Selective nonconformal deposition for forming low dielectric insulation between certain conductive lines | Darrell M. Erb, Robin Cheung, Rich Klein | 2000-04-11 |
| 6017463 | Point of use mixing for LI/plug tungsten polishing slurry to improve existing slurry | Christy Mei-Chu Woo, Steven Douglas Bartlett | 2000-01-25 |
| 5990557 | Bias plasma deposition for selective low dielectric insulation | Darrell M. Erb, Robin Cheung, Rich Klein, Pervaiz Sultan | 1999-11-23 |
| 5955786 | Semiconductor device using uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines | Darrell M. Erb, Robin Cheung, Rich Klein | 1999-09-21 |
| 5916855 | Chemical-mechanical polishing slurry formulation and method for tungsten and titanium thin films | Christy Mei-Chu Woo, Diana M. Schonauer, Peter A. Burke | 1999-06-29 |
| 5837618 | Uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines | Darrell M. Erb, Robin Cheung | 1998-11-17 |
| 5795823 | Self aligned via dual damascene | Subhash Gupta, Rich Klein, Scott Luning, Ming-Ren Lin | 1998-08-18 |
| 5776834 | Bias plasma deposition for selective low dielectric insulation | Darrell M. Erb, Robin Cheung, Rich Klein, Pervaiz Sultan | 1998-07-07 |
| 5770519 | Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device | Richard K. Klein, Darrell M. Erb, Robin Cheung, Scott Luning, Bryan Tracy +2 more | 1998-06-23 |
| 5705430 | Dual damascene with a sacrificial via fill | Subhash Gupta, Rich Klein, Scott Luning, Ming-Ren Lin | 1998-01-06 |
| 5691573 | Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines | Darrell M. Erb, Robin Cheung, Rich Klein | 1997-11-25 |
| 5691238 | Subtractive dual damascene | Subhash Gupta, Rich Klein, Scott Luning, Ming-Ren Lin | 1997-11-25 |
| 5686354 | Dual damascene with a protective mask for via etching | Subhash Gupta, Rich Klein, Scott Luning, Ming-Ren Lin | 1997-11-11 |
| 5665199 | Methodology for developing product-specific interlayer dielectric polish processes | Kashmir Sahota | 1997-09-09 |
| 5662769 | Chemical solutions for removing metal-compound contaminants from wafers after CMP and the method of wafer cleaning | Diana M. Schonauer | 1997-09-02 |
| 5646448 | Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device | Richard K. Klein, Darrell M. Erb, Robin Cheung, Scott Luning, Bryan Tracy +2 more | 1997-07-08 |
| 5639691 | Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device | Richard K. Klein, Darrell M. Erb, Robin Cheung, Scott Luning, Bryan Tracy +2 more | 1997-06-17 |
| 5614765 | Self aligned via dual damascene | Subhash Gupta, Rich Klein, Scott Luning, Ming-Ren Lin | 1997-03-25 |
| 5382547 | Void free oxide fill for interconnect spaces | Pervaiz Sultan | 1995-01-17 |
| 5116778 | Dopant sources for CMOS device | Jacob D. Haskell, Balaji Swaminathan | 1992-05-26 |