Issued Patents All Time
Showing 26–43 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7263600 | System and method for validating a memory file that links speculative results of load operations to register values | Benjamin T. Sander, Krishnan V. Ramani, Ramsey W. Haddad | 2007-08-28 |
| 7251710 | Cache memory subsystem including a fixed latency R/W pipeline | Roger D. Isaac, Rama S. Gopal, James K. Pickett, Michael Filippo | 2007-07-31 |
| 7197630 | Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation | Benjamin T. Sander | 2007-03-27 |
| 7133975 | Cache memory system including a cache memory employing a tag including associated touch bits | Roger D. Isaac | 2006-11-07 |
| 7133969 | System and method for handling exceptional instructions in a trace cache based processor | Gregory W. Smaus, James K. Pickett, Brian D. McMinn, Michael Filippo, Benjamin T. Sander | 2006-11-07 |
| 7124236 | Microprocessor including bank-pipelined cache with asynchronous data blocks | Teik-Chung Tan, Jerry D. Moench | 2006-10-17 |
| 7073026 | Microprocessor including cache memory supporting multiple accesses per cycle | — | 2006-07-04 |
| 7069411 | Mapper circuit with backup capability | Brian D. McMinn | 2006-06-27 |
| 7043626 | Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming | Brian D. McMinn, James K. Pickett | 2006-05-09 |
| 7003629 | System and method of identifying liveness groups within traces stored in a trace cache | — | 2006-02-21 |
| 6976147 | Stride-based prefetch mechanism using a prediction confidence value | Roger D. Isaac | 2005-12-13 |
| 6950925 | Scheduler for use in a microprocessor that supports data-speculative execution | Benjamin T. Sander, Michael Filippo | 2005-09-27 |
| 6690154 | High-frequency tester for semiconductor devices | Joe David Jones | 2004-02-10 |
| 5694564 | Data processing system a method for performing register renaming having back-up capability | Michael Becker | 1997-12-02 |
| 5367494 | Randomly accessible memory having time overlapping memory accesses | Michael C. Shebanow, Hunter Ledbetter Scales, III, George P. Hoekstra | 1994-11-22 |
| 5355457 | Data processor for performing simultaneous instruction retirement and backtracking | Michael C. Shebanow | 1994-10-11 |
| 5173617 | Digital phase lock clock generator without local oscillator | Carl S. Dobbs, Yung-Jung Wayne Wu, Claude Moughanni, Elie I. Haddad | 1992-12-22 |
| 4893267 | Method and apparatus for a data processor to support multi-mode, multi-precision integer arithmetic | Yoav Talgam, Marvin Denman | 1990-01-09 |