Issued Patents All Time
Showing 1–25 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12306773 | Multiprocessor system with improved secondary interconnection network | Michael R. Trocino | 2025-05-20 |
| 12197970 | Processing system with interspersed processors DMA-FIFO | Michael R. Trocino, Keith M. Bindloss | 2025-01-14 |
| 11900124 | Memory-network processor with programmable optimizations | Michael B. Doerr, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss +3 more | 2024-02-13 |
| 11829320 | Memory network processor | Keith M. Bindloss, Kenneth R. Faulkner, Alex E. Icaza, Frederick Rush, Faisal A. Syed +1 more | 2023-11-28 |
| 11755504 | Multiprocessor system with improved secondary interconnection network | Michael R. Trocino | 2023-09-12 |
| 11550750 | Memory network processor | Keith M. Bindloss, Kenneth R. Faulkner, Alex E. Icaza, Frederick Rush, Faisal A. Syed +1 more | 2023-01-10 |
| 11544072 | Memory-network processor with programmable optimizations | Michael B. Doerr, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss +3 more | 2023-01-03 |
| 11483580 | Distributed architecture for encoding and delivering video content | Michael W. Bruns, Michael B. Solka, Martin Hunt, Michael B. Doerr, Tommy K. Eng | 2022-10-25 |
| 11327753 | Processor instructions to accelerate FEC encoding and decoding | Keith M. Bindloss, Evgeny Mezhibovsky, Zahir Raza, Kevin A. Shelby | 2022-05-10 |
| 11030023 | Processing system with interspersed processors DMA-FIFO | Michael R. Trocino, Keith M. Bindloss | 2021-06-08 |
| 11016779 | Memory-network processor with programmable optimizations | Michael B. Doerr, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss +3 more | 2021-05-25 |
| 10838787 | Processing system with interspersed processors with multi-layer interconnect | Michael R. Trocino, Michael B. Solka | 2020-11-17 |
| 10747689 | Multiprocessor system with improved secondary interconnection network | Michael R. Trocino | 2020-08-18 |
| 10747709 | Memory network processor | Keith M. Bindloss, Kenneth R. Faulkner, Alex E. Icaza, Frederick Rush, Faisal A. Syed +1 more | 2020-08-18 |
| 10691451 | Processor instructions to accelerate FEC encoding and decoding | Keith M. Bindloss, Evgeny Mezhibovsky, Zahir Raza, Kevin A. Shelby | 2020-06-23 |
| 10685143 | Secure boot sequence for selectively disabling configurable communication paths of a multiprocessor fabric | Michael B. Doerr, Michael B. Solka, Michael R. Trocino, David A. Gibson | 2020-06-16 |
| 10521285 | Processing system with interspersed processors with multi-layer interconnection | Michael R. Trocino, Michael B. Solka | 2019-12-31 |
| 10185672 | Multiprocessor system with improved secondary interconnection network | Michael R. Trocino | 2019-01-22 |
| 10185608 | Processing system with interspersed processors with multi-layer interconnection | Michael R. Trocino, Michael B. Solka | 2019-01-22 |
| 10007806 | Secure boot sequence for selectively disabling configurable communication paths of a multiprocessor fabric | Michael B. Doerr, Michael B. Solka, Michael R. Trocino, David A. Gibson | 2018-06-26 |
| 10007293 | Clock distribution network for multi-frequency multi-processor systems | Michael R. Trocino, Kenneth R. Faulkner, Christopher L. Schreppel | 2018-06-26 |
| 9990241 | Processing system with interspersed processors with multi-layer interconnection | Michael R. Trocino, Michael B. Solka | 2018-06-05 |
| 9720867 | Processing system with interspersed processors with multi-layer interconnection | Michael R. Trocino, Michael B. Solka | 2017-08-01 |
| 9612984 | Multiprocessor system with improved secondary interconnection network | Michael R. Trocino | 2017-04-04 |
| 9558150 | Processing system with synchronization instruction | Afzal M. Malik, Kenneth R. Faulkner, Michael B. Solka | 2017-01-31 |