Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12197970 | Processing system with interspersed processors DMA-FIFO | Carl S. Dobbs, Michael R. Trocino | 2025-01-14 |
| 11900124 | Memory-network processor with programmable optimizations | Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner +3 more | 2024-02-13 |
| 11829320 | Memory network processor | Carl S. Dobbs, Kenneth R. Faulkner, Alex E. Icaza, Frederick Rush, Faisal A. Syed +1 more | 2023-11-28 |
| 11550750 | Memory network processor | Carl S. Dobbs, Kenneth R. Faulkner, Alex E. Icaza, Frederick Rush, Faisal A. Syed +1 more | 2023-01-10 |
| 11544072 | Memory-network processor with programmable optimizations | Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner +3 more | 2023-01-03 |
| 11327753 | Processor instructions to accelerate FEC encoding and decoding | Carl S. Dobbs, Evgeny Mezhibovsky, Zahir Raza, Kevin A. Shelby | 2022-05-10 |
| 11030023 | Processing system with interspersed processors DMA-FIFO | Carl S. Dobbs, Michael R. Trocino | 2021-06-08 |
| 11016779 | Memory-network processor with programmable optimizations | Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner +3 more | 2021-05-25 |
| 10747709 | Memory network processor | Carl S. Dobbs, Kenneth R. Faulkner, Alex E. Icaza, Frederick Rush, Faisal A. Syed +1 more | 2020-08-18 |
| 10691451 | Processor instructions to accelerate FEC encoding and decoding | Carl S. Dobbs, Evgeny Mezhibovsky, Zahir Raza, Kevin A. Shelby | 2020-06-23 |
| 9430369 | Memory-network processor with programmable optimizations | Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner +3 more | 2016-08-30 |
| 9424213 | Processing system with interspersed processors DMA-FIFO | Carl S. Dobbs, Michael R. Trocino | 2016-08-23 |
| 7428653 | Method and system for execution and latching of data in alternate threads | Duncan M. Fisher, Ching Long Su, Marty T. Budrovic, Rajiv Gupta | 2008-09-23 |
| 7266811 | Methods, systems, and computer program products for translating machine code associated with a first processor for execution on a second processor | Moataz A. Mohamed, Wade Guthrie | 2007-09-04 |
| 6684319 | System for efficient operation of a very long instruction word digital signal processor | Moataz A. Mohamed | 2004-01-27 |
| 5778241 | Space vector data path | Kenneth E. Garey, George A. Watson, John Earle | 1998-07-07 |
| 5586284 | Triple register RISC digital signal processor | Ricke W. Clark, Kenneth E. Garey, George A. Watson, Lawrence F. Blank | 1996-12-17 |
| 5544311 | On-chip debug port | Donald D. Harenberg, George A. Watson, Dale E. Folwell | 1996-08-06 |
| 5479626 | Signal processor contexts with elemental and reserved group addressing | Kenneth E. Garey, John Earle | 1995-12-26 |