Issued Patents All Time
Showing 51–68 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6400030 | Self-aligning vias for semiconductors | Fei Wang, Robin Cheung, Richard J. Huang, Angela T. Hui | 2002-06-04 |
| 6326310 | Method and system for providing shallow trench profile shaping through spacer and etching | Yowjuang W. Liu | 2001-12-04 |
| 6306706 | Method and system for fabricating a flash memory array | Maria C. Chan, Hao Fang | 2001-10-23 |
| 6249036 | Stepper alignment mark formation with dual field oxide process | Tatsuya Kajita | 2001-06-19 |
| 6232646 | Shallow trench isolation filled with thermal oxide | Yu Sun, Angela T. Hui, Yue-Song He, Tatsuya Kajita, Chi Chang +1 more | 2001-05-15 |
| 6200884 | Method for shaping photoresist mask to improve high aspect ratio ion implantation | Chih-Yuh Yang | 2001-03-13 |
| 6124201 | Method for manufacturing semiconductors with self-aligning vias | Fei Wang, Robin Cheung, Richard J. Huang, Angela T. Hui | 2000-09-26 |
| 6093967 | Self-aligned silicide contacts formed from deposited silicon | Yowjuang W. Liu, Michael K. Templeton | 2000-07-25 |
| 5965934 | Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS | Robin Cheung | 1999-10-12 |
| 5945352 | Method for fabrication of shallow isolation trenches with sloped wall profiles | Hung-Sheng Chen | 1999-08-31 |
| 5907781 | Process for fabricating an integrated circuit with a self-aligned contact | Hung-Sheng Chen, Unsoon Kim, Yu Sun, Chi Chang, Mark T. Ramsbey +4 more | 1999-05-25 |
| 5688717 | Construction that prevents the undercut of interconnect lines in plasma metal etch systems | Lewis Shen, Sheshadri Ramaswami, Robin Cheung | 1997-11-18 |
| 5679608 | Processing techniques for achieving production-worthy, low dielectric, low dielectric, low interconnect resistance and high performance IC | Robin Cheung | 1997-10-21 |
| 5675186 | Construction that prevents the undercut of interconnect lines in plasma metal etch systems | Lewis Shen, Sheshadri Ramaswami, Robin Cheung | 1997-10-07 |
| 5635423 | Simplified dual damascene process for multi-level metallization and interconnection structure | Richard J. Huang, Angela T. Hui, Robin Cheung, Ming-Ren Lin | 1997-06-03 |
| 5559055 | Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance | Robin Cheung | 1996-09-24 |
| 5550405 | Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS | Robin Cheung | 1996-08-27 |
| 4370405 | Multilayer photoresist process utilizing an absorbant dye | Michael O'Toole, En-Den D. Liu | 1983-01-25 |