Issued Patents All Time
Showing 201–225 of 265 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8187939 | Direct contact in trench with three-mask shield gate process | Sung-Shan Tai, Anup Bhalla, Hong Chang, John Chen | 2012-05-29 |
| 8148758 | High voltage semiconductor device with JFET regions containing dielectrically isolated junctions and method of fabricating the same | — | 2012-04-03 |
| 8063442 | Power device with improved edge termination | Daniel Calafut | 2011-11-22 |
| 8043913 | Method of forming trench-gate field effect transistors | Daniel Calafut, Christopher Boguslaw Kocon, Steven Sapp, Dean E. Probst, Nathan Kraft +5 more | 2011-10-25 |
| 7951688 | Method and structure for dividing a substrate into individual devices | Minhua Li, Qi Wang, Gordon Sim, Matthew Reynolds, Suku Kim +1 more | 2011-05-31 |
| 7943989 | Nano-tube MOSFET technology and devices | Daniel Ng, Lingpeng Guan, Anup Bhalla, Wilson Ma, Moses Ho +1 more | 2011-05-17 |
| 7923776 | Trench-gate field effect transistor with channel enhancement region and methods of forming the same | Daniel Calafut, Christopher Boguslaw Kocon, Steven Sapp, Dean E. Probst, Nathan Kraft +5 more | 2011-04-12 |
| 7910486 | Method for forming nanotube semiconductor devices | Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang | 2011-03-22 |
| 7884390 | Structure and method of forming a topside contact to a backside terminal of a semiconductor device | John T. Andrews, Bruce D. Marchant, Ihsiu Ho | 2011-02-08 |
| 7867855 | Method of fabricating high voltage semiconductor devices with JFET regions containing dielectrically isolated junctions | — | 2011-01-11 |
| 7863708 | Power device edge termination having a resistor with one end biased to source voltage | Daniel Calafut | 2011-01-04 |
| 7767524 | Method and structure for forming a shielded gate field effect transistor | Daniel Calafut, Steven Sapp, Nathan Kraft, Ashok Challa | 2010-08-03 |
| 7768075 | Semiconductor die packages using thin dies and metal substrates | Steven Sapp, Qi Wang, Minhua Li, James J. Murphy, John Robert Diroll | 2010-08-03 |
| 7768034 | Tapered voltage polysilicon diode electrostatic discharge circuit for power MOSFETs and ICs | Daniel Calafut, Steven Sapp | 2010-08-03 |
| 7635635 | Method for bonding a semiconductor substrate to a metal substrate | Qi Wang, Minhua Li, Chung-Lin Wu | 2009-12-22 |
| 7629631 | High voltage semiconductor devices with JFET regions containing dielectrically isolated junctions | — | 2009-12-08 |
| 7625799 | Method of forming a shielded gate field effect transistor | Daniel Calafut, Steven Sapp, Nathan Kraft, Ashok Challa | 2009-12-01 |
| 7553700 | Chemical-enhanced package singulation process | Anthony Chia, Xiaoguang Zeng, Wong Hie Ming, Liming Wang, Yiju Zhang | 2009-06-30 |
| 7521773 | Power device with improved edge termination | Daniel Calafut | 2009-04-21 |
| 7514322 | Shielded gate field effect transistor | Daniel Calafut, Steven Sapp, Nathan Kraft, Ashok Challa | 2009-04-07 |
| 7504303 | Trench-gate field effect transistors and methods of forming the same | Daniel Calafut, Christopher Boguslaw Kocon, Steven Sapp, Dean E. Probst, Nathan Kraft +5 more | 2009-03-17 |
| 7504306 | Method of forming trench gate field effect transistor with recessed mesas | Steven Sapp, Christopher L. Rexer, Daniel Calafut | 2009-03-17 |
| 7489011 | Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics | — | 2009-02-10 |
| 7427800 | Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics | — | 2008-09-23 |
| 7416948 | Trench FET with improved body to gate alignment | Nathan Kraft, Ashok Challa, Steven Sapp, Daniel Calafut, Dean E. Probst +5 more | 2008-08-26 |