Issued Patents All Time
Showing 226–250 of 265 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7405452 | Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics | — | 2008-07-29 |
| 7393749 | Charge balance field effect transistor | Daniel Calafut, Steven Sapp, Nathan Kraft, Ashok Challa | 2008-07-01 |
| 7382044 | Semiconductor device package diepad having features formed by electroplating | Anthony Chia, Seishi Fujimaki, Xiaoguang Zeng | 2008-06-03 |
| 7323386 | Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics | — | 2008-01-29 |
| 7122406 | Semiconductor device package diepad having features formed by electroplating | Anthony Chia, Seishi Fujimaki, Xiaoguang Zeng | 2006-10-17 |
| 6878993 | Self-aligned trench MOS junction field-effect transistor for high-frequency applications | — | 2005-04-12 |
| 6552889 | Current limiting technique for hybrid power MOSFET circuits | John Huang, Mohamed N. Darwish, Wharton McDaniel, Kyle Terrill, Peter Tu Dang | 2003-04-22 |
| 5770503 | Method of forming low threshold voltage vertical power transistor using epitaxial technology | Fwu-Iuan Hshieh, Mike F. Chang | 1998-06-23 |
| 5751054 | Zener diodes on the same wafer with BiCDMOS structures | Richard K. Williams, Michael E. Cornell, Jun-Wei Chen | 1998-05-12 |
| 5648281 | Method for forming an isolation structure and a bipolar transistor on a semiconductor substrate | Richard K. Williams, Michael E. Cornell, Jun-Wei Chen | 1997-07-15 |
| 5643820 | Method for fabricating an MOS capacitor using zener diode region | Richard K. Williams, Michael E. Cornell, Jun-Wei Chen | 1997-07-01 |
| 5618743 | MOS transistor having adjusted threshold voltage formed along with other transistors | Richard K. Williams, Michael E. Cornell, Jun-Wei Chen | 1997-04-08 |
| 5614751 | Edge termination structure for power MOSFET | Fwu-Iuan Hshieh | 1997-03-25 |
| 5597765 | Method for making termination structure for power MOSFET | Fwu-Iuan Hshieh | 1997-01-28 |
| 5583061 | PMOS transistors with different breakdown voltages formed in the same substrate | Richard K. Williams, Michael E. Cornell, Jun-Wei Chen | 1996-12-10 |
| 5559044 | BiCDMOS process technology | Richard K. Williams, Michael E. Cornell, Jun-Wei Chen | 1996-09-24 |
| 5547880 | Method for forming a zener diode region and an isolation region | Richard K. Williams, Michael E. Cornell, Jun-Wei Chen | 1996-08-20 |
| 5541125 | Method for forming a lateral MOS transistor having lightly doped drain formed along with other transistors in the same substrate | Richard K. Williams, Michael E. Cornell, Jun-Wei Chen | 1996-07-30 |
| 5541123 | Method for forming a bipolar transistor having selected breakdown voltage | Richard K. Williams, Michael E. Cornell, Jun-Wei Chen | 1996-07-30 |
| 5517379 | Reverse battery protection device containing power MOSFET | Richard K. Williams, Thomas N. Toombs, King Owyang | 1996-05-14 |
| 5479037 | Low threshold voltage epitaxial DMOS technology | Fwu-Iuan Hshieh, Mike F. Chang | 1995-12-26 |
| 5474943 | Method for fabricating a short channel trenched DMOS transistor | Fwu-Iuan Hshieh, Mike F. Chang | 1995-12-12 |
| 5445978 | Method of making power device with buffered gate shield region | — | 1995-08-29 |
| 5430314 | Power device with buffered gate shield region | — | 1995-07-04 |
| 5429964 | Low on-resistance power MOS technology | Fwu-Iuan Hshieh, Mike F. Chang, Jun-Wei Chen, King Owyang, Dorman C. Pitzer +1 more | 1995-07-04 |