Issued Patents 2024
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12176016 | Memory device having bitline segmented into bitline segments and related method for operating memory device | Shih-Lien Linus Lu, Yi-Chun Shih | 2024-12-24 |
| 12159791 | Info packages including thermal dissipation blocks | Ching-Yi Lin, Yu-Hao Chen, Po-Hsiang Huang, Jyh Chwen Frank Lee, Shuo-Mao Chen | 2024-12-03 |
| 12154842 | Heat dissipation structures for three-dimensional system on integrated chip structure | Po-Hsiang Huang, Chin-Chou Liu, Chin-Her Chien, Hui Yu Lee | 2024-11-26 |
| 12087690 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Chung-Hsing Wang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang +6 more | 2024-09-10 |
| 12079561 | Cell region including portion of conductor of another cell region and semiconductor device include the same | Chin-Chou Liu, Sheng-Hsiung Chen, Po-Hsiang Huang | 2024-09-03 |
| 12074148 | Heat dissipation in semiconductor packages and methods of forming same | Po-Hsiang Huang, Lee-Chung Lu, Jyh Chwen Frank Lee, Yii-Chian Lu, Yu-Hao Chen +1 more | 2024-08-27 |
| 12062641 | Integrated circuit including a first semiconductor wafer and a second semiconductor wafer, semiconductor device including a first semiconductor wafer and a second semiconductor wafer and method of manufacturing same | Chih-Lin Chen, Hui Yu Lee, Po-Hsiang Huang, Chin-Chou Liu | 2024-08-13 |
| 12056432 | Pin modification for standard cells | Chun-Chen Chen, Sheng-Hsiung Chen, Ting-Wei Chiang, Chung-Te Lin, Jung-Chan Yang +2 more | 2024-08-06 |
| 12027513 | Layout design methodology for stacked devices | Po-Hsiang Huang, Chin-Chou Liu, Chin-Her Chien, Ka Fai Chang | 2024-07-02 |
| 12009260 | Method and system of forming integrated circuit | Ka Fai Chang, Chin-Chou Liu, Yi-Kan Cheng | 2024-06-11 |
| 12002776 | Interconnect structure and method for forming the same | Jung-Chou Tsai, Po-Hsiang Huang, Chin-Chou Liu, Yi-Kan Cheng | 2024-06-04 |
| 11983475 | Method for manufacturing a cell having pins and semiconductor device based on same | Pin-Dai Sue, Po-Hsiang Huang, Chi-Yu Lu, Sheng-Hsiung Chen, Chin-Chou Liu +4 more | 2024-05-14 |
| 11967591 | Info packages including thermal dissipation blocks | Yu-Hao Chen, Po-Hsiang Huang, Ching-Yi Lin, Jyh Chwen Frank Lee | 2024-04-23 |
| 11942441 | Electrostatic discharge protection cell and antenna integrated with through silicon via | HoChe Yu, XinYong WANG, Chih-Liang Chen, Tzu-Heng Chang | 2024-03-26 |
| 11935894 | Integrated circuit device with improved layout | Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao +2 more | 2024-03-19 |
| 11929340 | Arrangement of power-grounds in package structures | Ting-Yu Yeh, Chun Hua Chang, Jyh Chwen Frank Lee | 2024-03-12 |
| 11923302 | Semiconductor device and method of manufacture | Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu +1 more | 2024-03-05 |
| 11923271 | 3D IC power grid | Noor Mohamed, Po-Hsiang Huang, Chin-Chou Liu | 2024-03-05 |
| 11908853 | Integrated circuit and method of generating integrated circuit layout | Kuo-Nan Yang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang +3 more | 2024-02-20 |
| 11861282 | Integrated circuit fin structure manufacturing method | Po-Hsiang Huang, Clement Hsingjen Wann, Chih-Hsin Ko, Sheng-Hsiung Chen, Li-Chun Tien +1 more | 2024-01-02 |