Issued Patents 2024
Showing 1–25 of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12185531 | 3D NOR type memory array with wider source/drain conductive lines | Yu-Wei Jiang, Sheng-Chih Lai, Feng-Cheng Yang | 2024-12-31 |
| 12178051 | Magnetic random access memory and manufacturing method thereof | Hui-Hsien Wei, Han-Ting Tsai, Tai-Yen Peng, Yu-Teng Dai, Chien-Min Lee +2 more | 2024-12-24 |
| 12176022 | Programming and reading circuit for dynamic random access memory | Chen-Jun Wu, Yun-Feng Kao, Sheng-Chih Lai, Katherine H. Chiang | 2024-12-24 |
| 12176286 | Memory device and method of forming the same | Li-Shyue Lai, Chien-Hao Huang, Chia-Yu Ling, Katherine H. Chiang | 2024-12-24 |
| 12171106 | Non-volatile memory with dual gated control | Katherine H. Chiang | 2024-12-17 |
| 12167609 | Semiconductor structure and method of forming the same | Min Dai, Yen-Chieh Huang, Kuo-Chang Chiang, Han-Ting Tsai, Tsann Lin | 2024-12-10 |
| 12167608 | Methods of forming three-dimensional memory devices | Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin | 2024-12-10 |
| 12154965 | Carrier barrier layer for tuning a threshold voltage of a ferroelectric memory device | Rainer Yen-Chieh Huang, Hai-Ching Chen, Yu-Ming Lin | 2024-11-26 |
| 12150309 | Double gate metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) structure | Yen-Chieh Huang, Po-Ting Lin, Song-Fu Liao, Hai-Ching Chen, Sai-Hooi Yeong +1 more | 2024-11-19 |
| 12150306 | Three-dimensional memory device and method | Chia-Yu Ling, Katherine H. Chiang | 2024-11-19 |
| 12148505 | Memory array staircase structure | Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin | 2024-11-19 |
| 12150311 | Embedded ferroelectric FinFET memory device | Bo-Feng Young, Sai-Hooi Yeong, Yu-Ming Lin, Sheng-Chih Lai, Chih-Yu Chang +1 more | 2024-11-19 |
| 12137566 | Peripheral circuitry under array memory device and method of fabricating thereof | Sheng-Chih Lai | 2024-11-05 |
| 12137573 | Self-aligned multilayer spacer matrix for high-density transistor arrays and methods for forming the same | Gao-Ming Wu, Katherine H. Chiang, Chien-Hao Huang | 2024-11-05 |
| 12137621 | Intercalated metal/dielectric structure for nonvolatile memory devices | Mauricio Manfrini, Gerben Doornbos, Marcus Johannes Henricus Van Dal | 2024-11-05 |
| 12136457 | Multinary bit cells for memory devices and network applications and method of manufacturing the same | Katherine H. Chiang | 2024-11-05 |
| 12127489 | Integrated circuit structure | Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee +2 more | 2024-10-22 |
| 12127411 | Cocktail layer over gate dielectric layer of FET FeRAM | Rainer Yen-Chieh Huang, Hai-Ching Chen | 2024-10-22 |
| 12125548 | Memory array test method and system | Chien-Hao Huang, Katherine H. Chiang, Cheng-Yi Wu | 2024-10-22 |
| 12125921 | Semiconducting metal oxide transistors having a patterned gate and methods for forming the same | Yong-Jie Wu, Hui-Hsien Wei, Yen-Chung Ho, Mauricio Manfrini, Chia-Jung Yu +1 more | 2024-10-22 |
| 12119402 | Semiconductor devices with ferroelectric layer and methods of manufacturing thereof | Yen-Chieh Huang, Po-Ting Lin, Hai-Ching Chen, Sai-Hooi Yeong, Yu-Ming Lin | 2024-10-15 |
| 12120884 | Semiconductor device and method of manufacturing the same | Chia-Yu Ling, Katherine H. Chiang | 2024-10-15 |
| 12114507 | Capping layer over FET FeRAM to increase charge mobility | Rainer Yen-Chieh Huang, Hai-Ching Chen | 2024-10-08 |
| 12113063 | Semiconductor device including vertical routing structure and method for manufacturing the same | Wei-Chih Wen, Han-Ting Tsai | 2024-10-08 |
| 12108605 | Memory device and method of forming the same | Chieh-Fang Chen, Feng-Cheng Yang | 2024-10-01 |