Issued Patents 2023
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11841617 | Method of forming a narrow trench | Anton J. deVilliers, Jodi Grzeskowiak, Daniel Fulford, Richard A. Farrell | 2023-12-12 |
| 11830852 | Multi-tier backside power delivery network for dense gate-on-gate 3D logic | Lars Liebmann, Daniel Chanemougame, Paul Gutwin, Brian Tracy Cline, Xiaoqing Xu +1 more | 2023-11-28 |
| 11791271 | Monolithic formation of a set of interconnects below active devices | Daniel Chanemougame, Lars Liebmann | 2023-10-17 |
| 11764266 | Three-dimensional semiconductor device | Lars Liebmann, Daniel Chanemougame, Paul Gutwin | 2023-09-19 |
| 11764113 | Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholds | Daniel Chanemougame, Lars Liebmann, Paul Gutwin, Robert D. Clark, Anton J. deVilliers | 2023-09-19 |
| 11742241 | ALD (atomic layer deposition) liner for via profile control and related applications | Xinghua Sun, Yen-Tien Lu, Angelique Raley, David L. O'Meara | 2023-08-29 |
| 11735525 | Power delivery network for CFET with buried power rails | Lars Liebmann, Anton J. deVilliers, Daniel Chanemougame | 2023-08-22 |
| 11705369 | Fully self-aligned via with selective bilayer dielectric regrowth | Kandabara Tapily | 2023-07-18 |
| 11676968 | Coaxial contacts for 3D logic and memory | Lars Liebmann, Anton J. deVilliers, Kandabara Tapily | 2023-06-13 |
| 11665878 | CFET SRAM bit cell with two stacked device decks | Daniel Chanemougame, Lars Liebmann | 2023-05-30 |
| 11656550 | Controlling semiconductor film thickness | Daniel Fulford, Michael Murphy, Jodi Grzeskowiak | 2023-05-23 |
| 11646318 | Connections from buried interconnects to device terminals in multiple stacked devices structures | Daniel Chanemougame, Lars Liebmann | 2023-05-09 |
| 11631671 | 3D complementary metal oxide semiconductor (CMOS) device and method of forming the same | H. Jim Fulford, Anton J. deVilliers, Mark I. Gardner, Daniel Chanemougame, Lars Liebmann +1 more | 2023-04-18 |
| 11616053 | Method to vertically route a logic cell incorporating stacked transistors in a three dimensional logic device | Anton J. deVilliers, Kandabara Tapily | 2023-03-28 |
| 11616020 | Power distribution network for 3D logic and memory | Lars Liebmann, Anton J. deVilliers, Kandabara Tapily | 2023-03-28 |
| 11581242 | Integrated high efficiency gate on gate cooling | Daniel Chanemougame, Lars Liebmann, Paul Gutwin | 2023-02-14 |
| 11574845 | Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices | Daniel Chanemougame, Lars Liebmann, Anton J. deVilliers | 2023-02-07 |
| 11545497 | CFET SRAM bit cell with three stacked device decks | Daniel Chanemougame, Lars Liebmann | 2023-01-03 |