Issued Patents 2023
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11854806 | Method for pattern reduction using a staircase spacer | Daniel Fulford | 2023-12-26 |
| 11848236 | Method for recessing a fill material within openings formed on a patterned substrate | Michael Murphy | 2023-12-19 |
| 11841617 | Method of forming a narrow trench | Jodi Grzeskowiak, Daniel Fulford, Richard A. Farrell, Jeffrey Smith | 2023-12-12 |
| 11810854 | Multi-dimensional vertical switching connections for connecting circuit elements | Mark I. Gardner, H. Jim Fulford | 2023-11-07 |
| 11782346 | Method of patterning a substrate using a sidewall spacer etch mask | Jodi Grzeskowiak, Anthony R. Schepis | 2023-10-10 |
| 11776808 | Planarization of spin-on films | Anthony R. Schepis | 2023-10-03 |
| 11776812 | Method for pattern reduction using a staircase spacer | Daniel Fulford | 2023-10-03 |
| 11764113 | Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholds | Jeffrey Smith, Daniel Chanemougame, Lars Liebmann, Paul Gutwin, Robert D. Clark | 2023-09-19 |
| 11735525 | Power delivery network for CFET with buried power rails | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame | 2023-08-22 |
| 11721551 | Localized stress regions for three-dimension chiplet formation | Daniel Fulford, Anthony R. Schepis, Mark I. Gardner, H. Jim Fulford | 2023-08-08 |
| 11721582 | Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits | Mark I. Gardner, H. Jim Fulford | 2023-08-08 |
| 11694957 | Programmable connection segment and method of forming the same | Mark I. Gardner, H. Jim Fulford | 2023-07-04 |
| 11688642 | Localized stress regions for three-dimension chiplet formation | Daniel Fulford, Anthony R. Schepis, Mark I. Gardner, H. Jim Fulford | 2023-06-27 |
| 11682559 | Method to form narrow slot contacts | Michael Murphy, Jodi Grzeskowiak | 2023-06-20 |
| 11676968 | Coaxial contacts for 3D logic and memory | Lars Liebmann, Jeffrey Smith, Kandabara Tapily | 2023-06-13 |
| 11640937 | Horizontal programmable conducting bridges between conductive lines | H. Jim Fulford, Mark I. Gardner | 2023-05-02 |
| 11640118 | Method of pattern alignment for field stitching | — | 2023-05-02 |
| 11631671 | 3D complementary metal oxide semiconductor (CMOS) device and method of forming the same | H. Jim Fulford, Mark I. Gardner, Daniel Chanemougame, Jeffrey Smith, Lars Liebmann +1 more | 2023-04-18 |
| 11630397 | Method for producing overlay results with absolute reference for semiconductor manufacturing | — | 2023-04-18 |
| 11616020 | Power distribution network for 3D logic and memory | Lars Liebmann, Jeffrey Smith, Kandabara Tapily | 2023-03-28 |
| 11616053 | Method to vertically route a logic cell incorporating stacked transistors in a three dimensional logic device | Jeffrey Smith, Kandabara Tapily | 2023-03-28 |
| 11574845 | Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices | Daniel Chanemougame, Lars Liebmann, Jeffrey Smith | 2023-02-07 |