Issued Patents 2023
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11804376 | Method for mitigating lateral film growth in area selective deposition | — | 2023-10-31 |
| 11769677 | Substrate processing tool with integrated metrology and method of using | Robert D. Clark | 2023-09-26 |
| 11705369 | Fully self-aligned via with selective bilayer dielectric regrowth | Jeffrey Smith | 2023-07-18 |
| 11700778 | Method for controlling the forming voltage in resistive random access memory devices | Steven P. Consiglio, Cory Wajda, Takaaki Tsunomura, Takashi Ando, Paul C. Jamison +3 more | 2023-07-11 |
| 11676968 | Coaxial contacts for 3D logic and memory | Lars Liebmann, Jeffrey Smith, Anton J. deVilliers | 2023-06-13 |
| 11658068 | Method of selective deposition for forming fully self-aligned vias | — | 2023-05-23 |
| 11658066 | Method for reducing lateral film formation in area selective deposition | — | 2023-05-23 |
| 11646227 | Method of forming a semiconductor device with air gaps for low capacitance interconnects | — | 2023-05-09 |
| 11621190 | Method for filling recessed features in semiconductor devices with a low-resistivity metal | Kai-Hung Yu, David L. O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert D. Clark +3 more | 2023-04-04 |
| 11616053 | Method to vertically route a logic cell incorporating stacked transistors in a three dimensional logic device | Jeffrey Smith, Anton J. deVilliers | 2023-03-28 |
| 11616020 | Power distribution network for 3D logic and memory | Lars Liebmann, Jeffrey Smith, Anton J. deVilliers | 2023-03-28 |
| 11594451 | Platform and method of operating for integrated end-to-end fully self-aligned interconnect process | Robert D. Clark, Kai-Hung Yu | 2023-02-28 |