| 11830852 |
Multi-tier backside power delivery network for dense gate-on-gate 3D logic |
Jeffrey Smith, Daniel Chanemougame, Paul Gutwin, Brian Tracy Cline, Xiaoqing Xu +1 more |
2023-11-28 |
| 11791271 |
Monolithic formation of a set of interconnects below active devices |
Daniel Chanemougame, Jeffrey Smith |
2023-10-17 |
| 11791263 |
Metallization lines on integrated circuit products |
Ruilong Xie, Daniel Chanemougame, Geng Han |
2023-10-17 |
| 11764266 |
Three-dimensional semiconductor device |
Jeffrey Smith, Daniel Chanemougame, Paul Gutwin |
2023-09-19 |
| 11764113 |
Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholds |
Jeffrey Smith, Daniel Chanemougame, Paul Gutwin, Robert D. Clark, Anton J. deVilliers |
2023-09-19 |
| 11735525 |
Power delivery network for CFET with buried power rails |
Jeffrey Smith, Anton J. deVilliers, Daniel Chanemougame |
2023-08-22 |
| 11723187 |
Three-dimensional memory cell structure |
Paul Gutwin, Daniel Chanemougame |
2023-08-08 |
| 11714945 |
Method for automated standard cell design |
— |
2023-08-01 |
| 11676968 |
Coaxial contacts for 3D logic and memory |
Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily |
2023-06-13 |
| 11665878 |
CFET SRAM bit cell with two stacked device decks |
Daniel Chanemougame, Jeffrey Smith |
2023-05-30 |
| 11646318 |
Connections from buried interconnects to device terminals in multiple stacked devices structures |
Daniel Chanemougame, Jeffrey Smith |
2023-05-09 |
| 11631671 |
3D complementary metal oxide semiconductor (CMOS) device and method of forming the same |
H. Jim Fulford, Anton J. deVilliers, Mark I. Gardner, Daniel Chanemougame, Jeffrey Smith +1 more |
2023-04-18 |
| 11621333 |
Gate contact structure for a transistor device |
Ruilong Xie, Hao Tang, Cheng Chi, Daniel Chanemougame, Mark V. Raymond |
2023-04-04 |
| 11616020 |
Power distribution network for 3D logic and memory |
Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily |
2023-03-28 |
| 11581242 |
Integrated high efficiency gate on gate cooling |
Daniel Chanemougame, Jeffrey Smith, Paul Gutwin |
2023-02-14 |
| 11574845 |
Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices |
Daniel Chanemougame, Jeffrey Smith, Anton J. deVilliers |
2023-02-07 |
| 11550985 |
Method for automated standard cell design |
— |
2023-01-10 |
| 11545497 |
CFET SRAM bit cell with three stacked device decks |
Daniel Chanemougame, Jeffrey Smith |
2023-01-03 |