Issued Patents 2023
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11854787 | Advanced lithography and self-assembled devices | Richard E. Schenker, Robert L. Bristol, Florian Gstrein, James M. Blackwell, Marie Krysak +6 more | 2023-12-26 |
| 11854882 | Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects | Robert L. Bristol, Richard E. Schenker | 2023-12-26 |
| 11830788 | Integrated circuits and methods for forming integrated circuits | Carl Naylor, Ashish Agrawal, Urusa Alaan, Christopher J. Jezewski, Mauro J. Kobrinsky +1 more | 2023-11-28 |
| 11830768 | Integrated circuits with line breaks and line bridges within a single interconnect level | Christopher J. Jezewski | 2023-11-28 |
| 11798838 | Capacitance reduction for semiconductor devices based on wafer bonding | Ehren Mannebach, Aaron D. Lilak, Rishabh Mehandru, Hui Jae Yoo, Patrick Morrow | 2023-10-24 |
| 11784121 | Integrated circuit components with dummy structures | Nicholas James Harold McKubre, Richard Vreeland, Sansaptak Dasgupta | 2023-10-10 |
| 11769814 | Device including air gapping of gate spacers and other dielectrics and process for providing such | Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Tristan A. Tronic | 2023-09-26 |
| 11764306 | Multi-layer crystalline back gated thin film transistor | Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack T. Kavalieros +6 more | 2023-09-19 |
| 11715791 | Group III-Nitride devices on SOI substrates having a compliant layer | Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Paul B. Fischer | 2023-08-01 |
| 11710636 | Metal and spacer patterning for pitch division with multiple line widths and spaces | Charles H. Wallace | 2023-07-25 |
| 11705395 | Core fill to reduce dishing and metal pillar fill to increase metal density of interconnects | — | 2023-07-18 |
| 11670588 | Selectable vias for back end of line interconnects | Christopher J. Jezewski, Ashish Agrawal, Abhishek A. Sharma, Carl Naylor, Urusa Alaan | 2023-06-06 |
| 11664305 | Staggered lines for interconnect performance improvement and processes for forming such | Manish Chandhok, Miriam Reshotko, Christopher J. Jezewski, Eungnak Han, Gurpreet Singh +2 more | 2023-05-30 |
| 11664270 | Metal-insulator-metal (MIM) structure supporting high voltage applications and low voltage applications | — | 2023-05-30 |
| 11646266 | Helmet structures for semiconductor interconnects | Miriam Reshotko, Nafees Kabir | 2023-05-09 |
| 11626451 | Magnetic memory device with ruthenium diffusion barrier | Emily Walker, Carl Naylor, Kaan Oguz, Tanay Gosavi, Christopher J. Jezewski +6 more | 2023-04-11 |
| 11616014 | Peripheral inductors | Paul B. Fischer | 2023-03-28 |
| 11605592 | Method to fabricate metal and ferromagnetic metal multilayer interconnect line for skin effect suppression | Noriyuki Sato, Kevin P. O'Brien, Hui Jae Yoo | 2023-03-14 |
| 11594485 | Local interconnect with air gap | Scott B. Clendenning, Tristan A. Tronic, Urusa Alaan, Ehren Mannebach | 2023-02-28 |
| 11557536 | Integrated circuits (IC's) with electro-migration (EM)—resistant segments in an interconnect level | Christopher J. Jezewski, Manish Chandhok | 2023-01-17 |