Issued Patents 2023
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11812599 | Compute near memory with backend memory | Abhishek A. Sharma, Noriyuki Sato, Sarah Atanasov, Huseyin Ekin Sumbul, Gregory K. Chen +3 more | 2023-11-07 |
| 11798838 | Capacitance reduction for semiconductor devices based on wafer bonding | Ehren Mannebach, Aaron D. Lilak, Rishabh Mehandru, Patrick Morrow, Kevin Lin | 2023-10-24 |
| 11769814 | Device including air gapping of gate spacers and other dielectrics and process for providing such | Ehren Mannebach, Aaron D. Lilak, Patrick Morrow, Kevin Lin, Tristan A. Tronic | 2023-09-26 |
| 11764263 | Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches | Ehren Mannebach, Anh Phan, Aaron D. Lilak, Willy Rachmady, Gilbert Dewey +3 more | 2023-09-19 |
| 11764104 | Forming an oxide volume within a fin | Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach +3 more | 2023-09-19 |
| 11699681 | Multi-chip module having a stacked logic chip and memory stack | Abhishek A. Sharma, Van H. Le, Huseyin Ekin Sumbul, Phil Knag, Gregory K. Chen +1 more | 2023-07-11 |
| 11672133 | Vertically stacked memory elements with air gap | Aaron D. Lilak, Patrick Morrow, Sean T. Ma, Scott B. Clendenning, Abhishek A. Sharma +2 more | 2023-06-06 |
| 11670545 | Conformal low temperature hermetic dielectric diffusion barriers | Sean King, Sreenivas Kosaraju, Timothy E. Glassman | 2023-06-06 |
| 11646352 | Stacked source-drain-gate connection and process for forming such | Ehren Mannebach, Aaron D. Lilak, Patrick Morrow, Anh Phan, Willy Rachmady +2 more | 2023-05-09 |
| 11640961 | III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts | Gilbert Dewey, Ravi Pillarisetty, Jack T. Kavalieros, Aaron D. Lilak, Willy Rachmady +6 more | 2023-05-02 |
| 11605592 | Method to fabricate metal and ferromagnetic metal multilayer interconnect line for skin effect suppression | Noriyuki Sato, Kevin Lin, Kevin P. O'Brien | 2023-03-14 |
| 11605565 | Three dimensional integrated circuits with stacked transistors | Cheng-Ying Huang, Willy Rachmady, Gilbert Dewey, Aaron D. Lilak, Kimin Jun +5 more | 2023-03-14 |
| 11594673 | Two terminal spin orbit memory devices and methods of fabrication | Noriyuki Sato, Angeline Smith, Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz +8 more | 2023-02-28 |
| 11587827 | Conformal low temperature hermetic dielectric diffusion barriers | Sean King, Sreenivas Kosaraju, Timothy E. Glassman | 2023-02-21 |
| 11574910 | Device with air-gaps to reduce coupling capacitance and process for forming such | Abhishek A. Sharma, Willy Rachmady, Van H. Le, Travis W. Lajoie, Urusa Alaan +2 more | 2023-02-07 |
| 11569238 | Vertical memory cells | Aaron D. Lilak, Willy Rachmady, Gilbert Dewey, Kimin Jun, Patrick Morrow +5 more | 2023-01-31 |
| 11569126 | Interconnect wires including relatively low resistivity cores | Tejaswi K. Indukuri, Ramanan V. Chebiam, James S. Clarke | 2023-01-31 |