Issued Patents 2022
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11538806 | Gate-all-around integrated circuit structures having high mobility | Roza Kotlyar, Rishabh Mehandru, Biswajeet Guha, Dax M. Crum, Tahir Ghani | 2022-12-27 |
| 11527640 | Wrap-around contact structures for semiconductor nanowires and nanoribbons | Rishabh Mehandru, Tahir Ghani, Biswajeet Guha | 2022-12-13 |
| 11527613 | Removal of a bottom-most nanowire from a nanowire device stack | Aaron D. Lilak, Patrick H. Keys, Sean T. Ma, Rishabh Mehandru | 2022-12-13 |
| 11527612 | Gate-all-around integrated circuit structures having vertically discrete source or drain structures | Glenn A. Glass, Anand S. Murthy, Biswajeet Guha, Dax M. Crum, Sean T. Ma +3 more | 2022-12-13 |
| 11521968 | Channel structures with sub-fin dopant diffusion blocking layers | Cory Bomberger, Anand S. Murthy, Biswajeet Guha, Anupama Bowonder, Tahir Ghani | 2022-12-06 |
| 11522072 | Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices | Rishabh Mehandru, Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim +1 more | 2022-12-06 |
| 11495672 | Increased transistor source/drain contact area using sacrificial source/drain layer | Dax M. Crum, Biswajeet Guha, William Hsu, Tahir Ghani | 2022-11-08 |
| 11495683 | Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed material | Aaron D. Lilak, Patrick H. Keys, Sayed Hasan, Anupama Bowonder | 2022-11-08 |
| 11430868 | Buried etch-stop layer to help control transistor source/drain depth | Rishabh Mehandru, Biswajeet Guha, Anupama Bowonder, Anand S. Murthy, Tahir Ghani | 2022-08-30 |
| 11404319 | Vertically stacked finFETs and shared gate patterning | Aaron D. Lilak, Sean T. Ma, Justin R. Weber, Rishabh Mehandru, Patrick Morrow +1 more | 2022-08-02 |
| 11374004 | Pedestal fin structure for stacked transistor integration | Aaron D. Lilak, Rishabh Mehandru, Anh Phan, Gilbert Dewey, Willy Rachmady +5 more | 2022-06-28 |
| 11367722 | Stacked nanowire transistor structure with different channel geometries for stress | Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Roza Kotlyar, Rishabh Mehandru +4 more | 2022-06-21 |
| 11335807 | Isolation schemes for gate-all-around transistor devices | Rishabh Mehandru, Biswajeet Guha, Tahir Ghani, William Hsu | 2022-05-17 |
| 11276780 | Transistor contact area enhancement | Rishabh Mehandru, Tahir Ghani | 2022-03-15 |
| 11276691 | Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths | Biswajeet Guha, Jun Sung Kang, Bruce Beattie, Tahir Ghani | 2022-03-15 |
| 11264500 | Device isolation | Rishabh Mehandru, Tahir Ghani | 2022-03-01 |