| 11495672 |
Increased transistor source/drain contact area using sacrificial source/drain layer |
Dax M. Crum, Biswajeet Guha, Stephen M. Cea, Tahir Ghani |
2022-11-08 |
| 11456357 |
Self-aligned gate edge architecture with alternate channel material |
Biswajeet Guha, Anupama Bowonder, Szuya S. Liao, Mehmet O. Baykan, Tahir Ghani |
2022-09-27 |
| 11404578 |
Dielectric isolation layer between a nanowire transistor and a substrate |
Bruce Beattie, Leonard P. GULER, Biswajeet Guha, Jun Sung Kang |
2022-08-02 |
| 11342411 |
Cavity spacer for nanowire transistors |
Biswajeet Guha, Leonard P. GULER, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie +1 more |
2022-05-24 |
| 11335807 |
Isolation schemes for gate-all-around transistor devices |
Rishabh Mehandru, Stephen M. Cea, Biswajeet Guha, Tahir Ghani |
2022-05-17 |
| 11302790 |
Fin shaping using templates and integrated circuit structures resulting therefrom |
Leonard P. GULER, Biswajeet Guha, Mark Armstrong, Tahir Ghani, Swaminathan Sivakumar |
2022-04-12 |
| 11233152 |
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices |
Biswajeet Guha, Leonard P. GULER, Dax M. Crum, Tahir Ghani |
2022-01-25 |