| 11538937 |
Fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material |
Nick Lindert, Biswajeet Guha, Swaminathan Sivakumar, Tahir Ghani |
2022-12-27 |
| 11527433 |
Via and plug architectures for integrated circuit interconnects and methods of manufacture |
Charles H. Wallace, Paul A. Nyhus |
2022-12-13 |
| 11404578 |
Dielectric isolation layer between a nanowire transistor and a substrate |
Bruce Beattie, Biswajeet Guha, Jun Sung Kang, William Hsu |
2022-08-02 |
| 11398474 |
Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions |
Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar |
2022-07-26 |
| 11355608 |
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures |
Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar |
2022-06-07 |
| 11342411 |
Cavity spacer for nanowire transistors |
William Hsu, Biswajeet Guha, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie +1 more |
2022-05-24 |
| 11302790 |
Fin shaping using templates and integrated circuit structures resulting therefrom |
Biswajeet Guha, Mark Armstrong, William Hsu, Tahir Ghani, Swaminathan Sivakumar |
2022-04-12 |
| 11251117 |
Self aligned gratings for tight pitch interconnects and methods of fabrication |
Manish Chandhok, Paul A. Nyhus, Gobind Bisht, Jonathan Laib, David Shykind +5 more |
2022-02-15 |
| 11233152 |
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices |
Biswajeet Guha, William Hsu, Dax M. Crum, Tahir Ghani |
2022-01-25 |
| 11227863 |
Gate isolation in non-planar transistors |
Gopinath Bhimarasetti, Vyom Sharma, Walid M. Hafez, Christopher P. Auth |
2022-01-18 |