Issued Patents 2022
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11538804 | Stacked integration of III-N transistors and thin-film transistors | Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer | 2022-12-27 |
| 11527532 | Enhancement-depletion cascode arrangements for enhancement mode III-N transistors | Nidhi Nidhi, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer +2 more | 2022-12-13 |
| 11521964 | Schottky diode structures and integration with III-V transistors | Han Wui Then, Paul B. Fischer, Marko Radosavljevic, Sansaptak Dasgupta | 2022-12-06 |
| 11515407 | High breakdown voltage structure for high performance GaN-based HEMT and MOS devices to enable GaN C-MOS | Glenn A. Glass, Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Paul B. Fischer +1 more | 2022-11-29 |
| 11502191 | Transistors with backside field plate structures | Johann Christian Rode, Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then | 2022-11-15 |
| 11489061 | Integrated programmable gate radio frequency (RF) switch | Han Wui Then, Marko Radosavljevic, Sansaptak Dusgupta, Paul B. Fischer | 2022-11-01 |
| 11450617 | Transmission line structures for III-N devices | Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Nidhi Nidhi, Paul B. Fischer +2 more | 2022-09-20 |
| 11444171 | Self-aligned gate endcap (SAGE) architecture having gate or contact plugs | Sairam Subramanian | 2022-09-13 |
| 11437483 | Gate-all-around integrated circuit structures having dual nanoribbon channel structures | Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Babak Fallahazad, Hsu-Yu Chang +2 more | 2022-09-06 |
| 11430873 | Self aligned gate connected plates for group III-Nitride devices and methods of fabrication | Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Paul B. Fischer | 2022-08-30 |
| 11424245 | Self-aligned gate endcap (SAGE) architecture having gate contacts | Sairam Subramanian | 2022-08-23 |
| 11404407 | Implants to enlarge Schottky diode cross-sectional area for lateral current conduction | Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Paul B. Fischer | 2022-08-02 |
| 11387327 | Silicide for group III-Nitride devices and methods of fabrication | Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Paul B. Fischer | 2022-07-12 |
| 11387328 | III-N tunnel device architectures and high frequency mixers employing a III-N tunnel device | Rahul Ramaswamy, Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then, Nidhi Nidhi | 2022-07-12 |
| 11387329 | Tri-gate architecture multi-nanowire confined transistor | Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer | 2022-07-12 |
| 11380679 | FET capacitor circuit architectures for tunable load and input matching | Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Nicholas James Harold McKubre | 2022-07-05 |
| 11362082 | Implanted substrate contact for in-process charging control | Han Wui Then, Paul B. Fischer, Marko Radosavljevic, Sansaptak Dasgupta | 2022-06-14 |
| 11342232 | Fabrication of Schottky barrier diode using lateral epitaxial overgrowth | Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Paul B. Fischer | 2022-05-24 |
| 11335800 | Work function based approaches to transistor threshold voltage tuning | Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer | 2022-05-17 |
| 11335601 | Non-planar I/O and logic semiconductor devices having different workfunction on common substrate | Roman W. Olac-Vaw, Chia-Hong Jan, Pei-Chi Liu | 2022-05-17 |
| 11329132 | Transistor with polarization layer superlattice for target threshold voltage tuning | Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Paul B. Fischer | 2022-05-10 |
| 11329138 | Self-aligned gate endcap (SAGE) architecture having endcap plugs | Sairam Subramanian, Christopher KENYON, Sridhar Govindaraju, Chia-Hong Jan, Mark Liu +1 more | 2022-05-10 |
| 11289483 | Metal fuse and self-aligned gate edge (SAGE) architecture having a metal fuse | Rohan K. Bambery, Mong-Kai Wu | 2022-03-29 |
| 11276760 | Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same | Gopinath Bhimarasetti, Joodong Park, Weimin Han, Raymond E. Cotner, Chia-Hong Jan | 2022-03-15 |
| 11251201 | High voltage three-dimensional devices having dielectric liners | Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti | 2022-02-15 |