Issued Patents 2022
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11507374 | True/false vector index registers and methods of populating thereof | — | 2022-11-22 |
| 11500665 | Dynamic configuration of a computer processor based on the presence of a hypervisor | — | 2022-11-15 |
| 11481241 | Virtual machine register in a computer processor | — | 2022-10-25 |
| 11481221 | Separate branch target buffers for different levels of calls | — | 2022-10-25 |
| 11436156 | Memory access control through permissions specified in page table entries for execution domains | — | 2022-09-06 |
| 11422820 | Shadow cache for securing conditional speculative instruction execution | — | 2022-08-23 |
| 11403226 | Cache with set associativity having data defined cache sets | — | 2022-08-02 |
| 11403107 | Protection against timing-based security attacks by randomly adjusting reorder buffer capacity | — | 2022-08-02 |
| 11403256 | Conditional operations in a vector processor having true and false vector index registers | — | 2022-08-02 |
| 11372648 | Extended tags for speculative and normal executions | — | 2022-06-28 |
| 11360777 | Cache systems and circuits for syncing caches or cache sets | — | 2022-06-14 |
| 11340904 | Vector index registers | — | 2022-05-24 |
| 11327862 | Multi-lane solutions for addressing vector elements using vector index registers | — | 2022-05-10 |
| 11307861 | Securing conditional speculative instruction execution | — | 2022-04-19 |
| 11275587 | Static identifications in object-based memory access | — | 2022-03-15 |
| 11237970 | Reduce data traffic between cache and memory via data access of variable sizes | — | 2022-02-01 |