Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed material

Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed material

US Patent 11495683 · Granted Nov 8, 2022

Estimated economic value: $15,080,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Double-sided integrated circuit transistor structures with depopulated bottom ch2025
Gate-all-around integrated circuit structures having underlying dopant-diffusion2025
Source or drain structures with relatively high germanium content2025
Reduced contact resistivity with PMOS germanium and silicon doped with boron gat2025
Fin shaping and integrated circuit structures resulting therefrom2025
Device, method and system to provide a stressed channel of a transistor2025
Gate-all-around integrated circuit structures having high mobility2025
3D 1T1C stacked dram structure and method to fabricate2025
Vertical integration scheme and circuit elements architecture for area scaling o2025
Gate-all-around integrated circuit structures having insulator substrate2025
Amorphization and regrowth of source-drain regions from the bottom-side of a sem2025
Backside contact structures and fabrication for metal on both sides of devices2025